Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.     

The influence of oxidation-sirtl etch condition on the stacking fault generation in (111) silicon wafers

The successive oxidation-Sirtl etch technique has been investigated to evaluate the perfection of silicon crystals by detecting extrinsic stacking faults produced during oxidation. Experiments were performed in (111) epitaxial wafers. Measured densities of stacking faults were found to epend on the conditions of thermal oxidation, and stacking fault densities were a maximum at an oxidation temperature of around 1100°C. The stacking fault densities were reduced appreciably when epitaxial wafers were chemically etched to remove several tens of microns prior to the test. The generation of stacking faults is thought to occur by heterogeneous nucleation due to a very small amount of unidentified impurity found in epitaxial crystals.     

The properties of annealed AlN films deposited by pulsed laser deposition

AlN films deposited on SiC or sapphire substrates by pulsed laser deposition were annealed at 1200°C, 1400°C, and 1600°C for 30 min in an inert atmosphere to examine how their structure, surface morphology, and substrate-film interface are altered during high temperature thermal processing. Shifts in the x-ray rocking curve peaks suggest that annealing increases the film density or relaxes the films and reduces the c-axis Poisson compression. Scanning electron micrographs show that the AlN begins to noticeably evaporate at 1600°C, and the evaporation rate is higher for the films grown on sapphire because the as-deposited film contained more pinholes. Rutherford backscattering spectroscopy shows that the interface between the film and substrate improves with annealing temperature for SiC substrates, but the interface quality for the 1600°C anneal is poorer than it is for the 1400°C anneal when the substrate is sapphire. Transmission electron micrographs show that the as-deposited films on SiC contain many stacking faults, while those annealed at 1600°C have a columnar structure with slightly misoriented grains. The as-deposited films on sapphire have an incoherent interface, and voids are formed at the interface when the samples are annealed at 1600°C. Auger electron spectroscopy shows that virtually no intermixing occurs across the interface, and that the annealed films contain less oxygen than the as-grown films.     

Thermal Annealing and Propagation of Shockley Stacking Faults in 4H-SiC PiN Diodes

Stacking faults within 4H-SiC PiN diodes are known to be detrimental to device operation. Here, we present electroluminescence (EL) images of 4H-SiC PiN diodes providing evidence that electrically and optically stimulated Shockley stacking fault (SSF) propagation is a reversible process at temperatures as low as 210°C. Optical beam induced current (OBIC) images taken following complete optical stressing of a PiN diode and that lead to a small number of completely propagated SSFs provide evidence that such defects propagate across the n–/p+ interface and continue to grow throughout the p+ layer. These observations bring about questions regarding the validity of the currently accepted driving force mechanism for SSF propagation.     

Rapid thermal nitridation of thin SiO2 films

An alternative to SiO₂ for gate dielectric applications in MIS devices is nitrided silicon dioxide. A study of this material is presented in this paper. Thin SiO₂ layers (10 nm minimum thickness) were grown on silicon substrates and subsequently nitrided in ammonia at 1 atm using a rapid thermal processing system. Nitridation times ranged from 3 sec to 60 sec at temperatures from 900 to 1200‡ C. The resulting films were then characterized using a variety of techniques including high resolution TEM, XPS, AES, SIMS, and electrical measurements (C-V). Higher temperatures and longer processing times resulted in the accumulation of nitrogen at the film surface and at the Si/SiO₂ interface. As expected, the electrical characteristics of the nitrided films were strongly influenced by the processing conditions. The morphology of the interface, as revealed by high-resolution TEM, was also altered by the nitridation process, especially for high processing temperatures (>1000° C).     

The effect of high temperature annealing on the spatial variation of bulk lifetime near the SiSiO2 interface

In this paper, the effect of high temperature N₂ annealing at 1100°C on the minority carrier lifetime in the bulk of the silicon close to the SiSiO₂ interface has been investigated for dry thermal oxides and TCE oxides. This annealing results in substantial reduction of lifetime for dry thermal oxides and the same annealing process enhances the lifetime for TCE oxides. The annealing-affected region in silicon near the interface was scanned by computing lifetime as a function of distance from the SiSiO₂ interface, using the Zerbst method with a suitable modification. The smaller values of lifetime observed near the SiSiO₂ interface have been correlated with stacking faults whose electrical activity seems to be significantly controlled by metallic impurities. A mechanism (supported by the experimental results) is suggested for the lifetime change due to annealing. The influx of metallic impurities coming from the annealing ambient seems to be decreasing the lifetime of carriers in silicon under dry thermal oxides, whereas, for the TCE oxides, we postulate that chlorine incorporated in the oxides prevents this influx and further also helps in the deactivation of existing metallic impurities in the silicon.     

Defects in the crystal structure of Cd<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>Hg<Subscript>1 − <Emphasis Type="Italic">x</Emphasis></Subscript>Te layers grown on the Si (310) substrates

Microstructure of the CdTe (310) and CdHgTe (310) layers grown by molecular-beam epitaxy on Si substrates has been studied by the methods of transmission electron microscopy and selective etching. It is established that formation of antiphase domains in the CdHgTe/CdTe/ZnTe/Si(310) is determined by the conditions of formation of the ZnTe/Si interface. Monodomain layers can be obtained by providing conditions that enhance zinc adsorption. An increase in the growth temperature and in the pressure of Te₂ vapors gives rise to antiphase domains and induces an increase in their density to the extent of the growth of poly-crystals. It is found that stacking faults exist in a CdHgTe/Si(310) heterostructure; these defects are anisotropically distributed in the bulk of grown layers. The stacking faults are predominantly located in one (111) plane, which intersects the (310) surface at an angle of 68°. The stacking faults originate at the ZnTe/Si(310) interface. The causes of origination of stacking faults and of their anisotropic distribution are discussed.     

Characterization of sputtered nano-crystalline zirconium carbide as a diffusion barrier for Cu metallization

Zirconium carbide (ZrC) films were grown on Si (100) substrates using magnetron sputtering where the growth temperature (T_s) was varied from 25°C to 290°C. The microstructure and resistivity of the as-deposited ZrC films were examined. The results reveal that nano-crystalline ZrC films with grain size less than 5 nm were fabricated only at 29°C, which can be explained by a repeated nucleation mechanism. For thermal stability characterization, the stacked structure of Cu/ZrC/Si was subsequently subject to thermal treatments at temperatures from 300°C to 900°C for 30 min in a vacuum tube. The stacked samples were shown to be thermally stable up to about 800°C from Auger electron spectroscopy (AES) and x-ray diffraction (XRD). The diffusion coefficient and activation energy of Cu and Si in the ZrC barrier were also derived. It indicated that Si has a lower activation energy than Cu resulting in faster diffusion. The device completely fails at 900°C, and the mechanism is discussed in this paper.     

Structural characterization of low temperature Epi-silicon grown on {100} and {111} Si substrates using ultrahigh resolution cross-sectional TEM

Low defect-density epitaxial silicon was grown at 550°C, but it became polysilicon or amorphous silicon when the substrate was submitted to bombardment of ECR argon plasma prior to growth. Through carefully characterizing the interface and structure of low temperature epitaxial silicon films using ultrahigh resolution cross-sectional transmission electron microscopy (UHRXTEM), defects were found to have different features in silicon epitaxial layers grown on {100} and {111} silicon substrates. Twinning was more likely to generate in the epitaxial layer grown on the {111} silicon substrate while stacking faults had priority in forming in the epitaxial layer grown on the {100} substrate. The probable causes of different defect formation mechanisms were analyzed and discussed with the help of UHRXTEM lattice images. The atom model of the twin boundary in the epitaxial silicon film was analyzed in detail.     

Analysis of persistent photoconductivity due to potential barriers

Persistent photoconductivity has been seen in thin silicon resistors fabricated with SIMOX material at temperatures between 60 and 220 K. This effect has been attributed to the depletion of carriers near the interface between the top silicon layer and the buried oxide, which is due to the large number of surface traps at this interface. The depletion of carriers is accompanied by a built-in field on the order of 10,000 V/cm, which causes a potential barrier that is nearly a quarter of the energy gap of silicon. The theory of the recombination kinetics of majority carriers with minority carriers trapped at the interface on the other side of a potential barrier is studied. Both the possibilities of tunneling and thermal activation have been considered. The results show that thermal activation dominates at the temperatures of our measurements in SIMOX material, while at lower temperatures tunneling would dominate.     

An X-ray Radiography Study of the Effect of Thermal Cycling on Damage Evolution in Large-Area Sn-3.5Ag Solder Joints

There is a need for next-generation, high-performance power electronic packages and systems utilizing wide-band-gap devices to operate at high temperatures in automotive and electricity transmission applications. Sn-3.5Ag solder is a candidate for use in such packages with potential maximum operating temperatures of about 200°C. However, there is a need to understand the thermal cycling reliability of Sn-3.5Ag solders subject to such high-temperature operating conditions. The results of a study on the damage evolution occurring in large-area Sn-3.5Ag solder joints between silicon dies and direct bonded copper substrates with Au/Ni-P metallization subject to thermal cycling between 200°C and 5°C are presented in this paper. Interface structure evolution and damage accumulation were followed using high-resolution X-ray radiography, cross-sectional optical and scanning electron microscopies, and X-ray microanalysis in these joints for up to 3000 thermal cycles. Optical and scanning electron microscopy results showed that the stresses introduced by the thermal cycling result in cracking and delamination at the copper–intermetallic compound interface. X-ray microanalysis showed that stresses due to thermal cycling resulted in physical cracking and breakdown of the Ni-P barrier layer, facilitating Cu-Sn interdiffusion. This interdiffusion resulted in the formation of Cu-Sn intermetallic compounds underneath the Ni-P layer, subsequently leading to delamination between the Ni-rich layer and Cu-Sn intermetallic compounds.     

Ultrathin PECVD epitaxial Si solar cells on glass via low‐temperature transfer process

Fabrication of high‐quality ultrathin monocrystalline silicon layers and their transfer to low‐cost substrates are key steps for flexible electronics and photovoltaics. In this work, we demonstrate a low‐temperature and low‐cost process for ultrathin silicon solar cells. By using standard plasma‐enhanced chemical vapor deposition (PECVD), we grow high‐quality epitaxial silicon layers (epi‐PECVD) from SiH₄/H₂ gas mixtures at 175 °C. Using secondary ion mass spectrometry and transmission electron microscopy, we show that the porosity of the epi‐PECVD/crystalline silicon interface can be tuned by controlling the hydrogen accumulation there. Moreover, we demonstrate that 13–14% porosity is a threshold above which the interface becomes fragile and can easily be cleaved. Taking advantage of the H‐rich interface fragility, we demonstrate the transfer of large areas (∽10 cm²) ultrathin epi‐PECVD layers (0.5–5.5 µm) onto glass substrates by anodic bonding and moderate annealing (275–350 °C). The structural properties of transferred layers are assessed, and the first PECVD epitaxial silicon solar cells transferred on glass are characterized. Copyright © 2016 John Wiley & Sons, Ltd.     

Thermal degeneration of Mo and Pt silicon Schottky diodes

In order to gain thermal stability and process compatibility, Mo and Pt silicon Schottky diodes have been annealed in an hydrogen atmosphere. A clear degeneration of the rectifying characteristics has been observed upon 450°C for Mo and 650°C for Pt.Although metal or defect diffusion could not be detected by transient capacitance measurements, the annealed devices did show anomalously high currents at low bias and at low temperatures. This excess current can be tentatively explained in terms of resonant tunnelling via deep centers near the interface metal-semiconductor induced by the annealing.The difference in the critical temperature for degeneration has its origin in the different behaviour of both barrier metals with silicon. While, in the case of platinum it seems that the silicide formation takes place at temperatures below 650°C with a subsequent diffusion of platinum or silicon vacancies into the silicon, in the case of molybdenum, the defect or metallic difusion apparently occurs before the silicide formation.     

Low temperature annealing behaviors of the titanium films formed by the ionized sputtering process on (001) silicon substrates

We investigated the low temperature reactions between the Ti films created by the ionized sputtering process and the (001) single crystal silicon wafers using high resolution transmission electron microscopy and x-ray diffractometry. We observed that the amorphous Ti-Si intermixed layer is formed at the Ti-Si interface whose thickness increased with the thickness of the deposited Ti films. The amorphous interlayer grew upon annealing treatments at the temperatures below 450°C. We also observed that the crystallization of the amorphous interlayer occurred upon annealing at 500°C. The first formed phase is Ti₅Si₃ in contact with Ti films, which is epitaxial with Ti films. Upon further annealing at 500°C, the Ti₅Si₄ phase and C49 TiSi₂ phase formed in the regions close to Ti films and Si substrates, respectively.     

Growth and characterization of ZnO thin films on GaN epilayers

Dense ZnO(0001) films formed at 500°C via coalescence of islands grown via metalorganic vapor phase epitaxy (MOVPE) either on GaN/AlN/SiC(0001) substrates or on initial, coherent ZnO layers. Conical crystallites formed due to thermal expansion-induced stresses between the ZnO and the substrate. Interfaces between the ZnO films on GaN epilayers exposed either simultaneously to diethylzinc and oxygen or only to diethylzinc at the initiation of growth were sharp and epitaxial. Interfaces formed after the exposure of the GaN to O₂ were less coherent, though an interfacial oxide was not observed by cross-sectional transmission electron microscopy (TEM). Threading dislocations and stacking faults were observed in all films.     

Structural characterization of oxide layers thermally grown on 3C-SiC films

The oxidation of 3C-SiC films deposited on off-oriented Si(001) substrates by reactive magnetron sputtering has been studied. The oxidation was carried out using dry conditions at a temperature of 1200°C. The composition of the oxide layer was investigated by Auger electron spectroscopy (AES). The oxide layer was found to contain no C except for the region very close to the interface, and the stoichiometry was found to be close to that of SiO₂. Cross-sectional transmis-sion electron microscopy (XTEM) showed the oxide layer to be completely amorphous, dense, and homogeneous with a uniform thickness. High-resolution XTEM imaging showed an atomically sharp SiO₂/SiC interface.     

Preparation of PbTiO3 thin films by plasma enhanced MOCVD and the effect of rapid thermal annealing

Dielectric PbTiO₃-thin films were prepared on p-Si(100) substrate by plasma enhanced metalorganic chemical vapor deposition using high purity Ti(O-i-C₃H₇)₄, Pb(tmhd)₂, and oxygen. As-deposited films were post-treated by rapid thermal annealing method, and the effect of annealing was examined under various conditions. The deposition process was controlled by mixed-control scheme at temperatures lower than 350°C, but controlled by heterogeneous surface reaction at temperatures greater than 350°C. The as-deposited films showed PbO structure at 350∼400°C, but (100) and (101) PbTiO₃ orientations started to appear at 450°C. The deposition rate was increased with rf power due to the enhanced dissociation of Ti and Pb precursors. It was found that the concentration of oxygen plays an important role in crystallization of PbTiO₃ during the rapid thermal annealing. A linear relationship was obtained between the dielectric constant of PbTiO₃ films and the annealing temperature. However, the surface roughness and leakage current density increased mainly due to the defects caused by volatilization of lead and the interface layer formed during the high temperature annealing.     

Optimization of saturation current density of PECVD SiN coated phosphorus diffused emitters using neural network modeling

Emitter surface passivation by low temperature plasma enhanced chemical vapor deposition (PECVD) silicon nitride is investigated and optimized in this paper. We have found that the saturation current density of a 90±10 μ/sq phosphorus diffused emitter with N_s ≈3 x 10¹⁹ and X_j ≈0.3 μm can be lowered by a factor of eight by appropriate PECVD silicon nitride deposition and photoassisted anneal. PECVD silicon nitride deposition alone reduces the emitter saturation density (J_oe) by about a factor of two to three, and a subsequent photoanneal at temperatures ≥350°C reduces J_oe by another factor of three. In spite of the larger flat band shift for direct PECVD silicon nitride coating, the silicon nitride induced surface passivation is found to be about a factor of two inferior to the thermal oxide plus PECVD silicon nitride passivation due to higher interface state density at the SiN/SiO₂ interface compared to SiO₂/Si interface. A combination of statistical experimental design and neural network modeling is used to show quantitatively that lower radio frequency power, higher substrate temperature, and higher reactor pressure during the PECVD deposition can reduce the J_oe of the silicon nitride coated emitter.     

Rapid thermal processing of thin gate dielectrics. Oxidation of silicon

A new rapid process for the growth of thin thermal oxide films on crystalline silicon is described. This rapid thermal oxidation (RTO) is performed in a controlled oxygen ambient with the heating provided by tungsten-halogen lamps. The resulting oxides with thicknesses from 40-130 Å have a uniformity of better than 2 percent across the 75-mm wafers. Oxidation times at 1150°C vary from 5 to 30 s. Typical breakdown fields of 100-Å oxide films were 13.8 MV/cm and typical midgap interface state densities were of the order of 1 × 10¹⁰eV^-1cm^-2. The present RTO films have characteristics equal to or better than furnace grown oxides and because of the short temperature-time cycle they have potential applications for submicrometer VLSI.     

Examination of In-Grown Stacking Faults in 8°- and 4°-Offcut 4H-SiC Epitaxy by Photoluminescence Imaging

Thirty-six large, up to 3-inch-diameter, epitaxial 4H-SiC samples were mapped by photoluminescence imaging. In-grown stacking faults (IGSFs) for both 8°- and 4°-offcut were examined structurally and spectrally. Imaging at various spectral bands revealed different features for IGSFs. For the 8°-offcut, IGSFs possessed two well-defined shapes, while for the 4°-offcut IGSFs appear with a variety of shapes. The difference in IGSF formations between 8°- and 4°-offcut is currently unknown. Screw dislocations displaced the IGSF basal plane, producing line defects that possessed irregular intensity. Rough estimates of the IGSF density were performed over representative regions of the whole wafers with some wafers having <1 cm⁻² while others had >100 cm⁻². Most IGSFs (>95%) originated at the epilayer/substrate interface, revealed by a small triangle in the buffer layer. Particles were responsible for the few IGSFs formed after the initial growth. The results suggested that pregrowth treatment and initial growth conditions were responsible for forming a majority of the IGSFs.