Model and analysis of gate leakage current in ultrathin nitridedoxide MOSFETs

An analytical model of the gate leakage current in ultrathin gate nitrided oxide MOSFETs is presented. This model is based on an inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical gate leakage current formulation. The tunneling-in and tunneling-out current are calculated by modifying the expression of the direct tunneling current model of BSIM. For a microscopic interpretation of the ITAT process, resonant tunneling (RT) through the oxide barrier containing potential wells associated with the localized states is proposed. We employ a quantum-mechanical model to treat electronic transitions within the trap potential well. The ITAT current model is then quantitatively consistent with the summation of the resonant tunneling current components of resonant energy levels. The 1/f noise observed in the gate leakage current implies the existence of slow processes with long relaxation times in the oxide barrier. In order to verify the proposed ITAT current model, an accurate method for determining the device parameters is necessary. The oxide thickness and the interface trap density of the gate oxide in the 20-30 Å thickness range are evaluated by the quasi-static capacitance-voltage (C-V) method, dealing especially with quantum-mechanical and polysilicon effects     

Submicrometer thin gate oxide P-channel transistors with P+polysilicon gates for VLSI applications

Submicrometer p-channel transistors have been fabricated using thin (150 Å) gate oxide and p+ polysilicon gates. Favorable device characteristics have been achieved for L(eff) as low as 0.4 µm. P+ gate was formed under different processing conditions. Data showed negligible boron penetration through the thin oxide. Two-dimensional simulations demonstrated the advantages of p+ poly in reducing short channel effects. Experimental results from three device lots with different processing conditions showed good subthreshold slope and low leakage current, even for low threshold voltages. VTversus L(eff) showed much less threshold drop than was seen using n+ poly. Device characteristics were robust with respect to processing variations.     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

Localized oxide degradation in ultrathin gate dielectric and its statistical analysis

Conventional oxide reliability studies determine oxide lifetime by measuring the time to breakdown or quasi-breakdown (QB). In ultrathin gate oxides with T/sub ox/<14 /spl Aring/, however, it is hard to observe breakdown or QB under typical stress conditions. Instead, the gate leakage current shows a continuous increase over the entire time period of electrical stress. As the magnitude of the gate current density increase eventually becomes too high to be acceptable for normal device operation, a lifetime criterion based on the increase in gate leakage current is proposed. Our paper also shows that the area-dependence of the gate leakage current density increase in 13.4 /spl Aring/ oxides is different from that in thicker oxide films, indicating a localized and discrete property of the leakage current. It has also been observed that the oxide lifetime based on the new lifetime criterion is shorter when the gate area is smaller, as opposed to the conventional area dependence of time-to-breakdown test. A simple model consisting of multiple degraded spots is proposed and it has been shown that localized gate leakage current can be described by Weibull's statistics for multiple degraded spots.     

Metal gate work function engineering on gate leakage of MOSFETs

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.     

Plasma-Induced Damage in High-k/Metal Gate Stack Dry Etch

Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

A multiple-terminal gate charging model

A gate charging model considering charging effect at all terminals of a MOSFET is reported in this letter. The model indicates two distinct charging mechanisms existing in P MOSFETs with a protecting device at their gates during plasma processing. The "normal-mode" charging mechanism exists when antenna size at the gate is higher than that at other terminals combined. In contrast, the "reverse-mode" charging mechanism exists in the case of antenna size at the gate lower than that at other terminals combined. The normal-mode mechanism will dominate the charging event when there is no protecting device at the transistor gate or the protecting device provides very low leakage current. On the other hand, the reverse-mode mechanism becomes dominant if the protecting device provides very high leakage current. The normal-mode charging mechanism is limited by the N-well junction leakage while in the reverse-mode mechanism, it is limited by the leakage of the protecting device. The model also suggests that larger N-well junction gives rise to higher charging damage in the normal-mode mechanism while it is opposite in the reverse-mode mechanism. These were confirmed by experimental data. The model points out that a zero charging damage can be achieved at certain combinations of the gate, source, drain and N-well antenna ratio. The knowledge of these transistor terminal antenna-ratio combinations will maximize the effective usage of the charging protection devices in circuit design. The reverse-mode charging mechanism suggests that the use of a high-leakage device at the transistor gate for charging protection may cause an opposite effect when the transistor terminal antenna ratios run into a condition that triggers this mechanism. This implies that PMOS transistors with gate intentionally pinned at ground or low potential in circuits may be prone to charging damage depending on the connectivity of their source, drain, and NW.     

Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr₂O₃) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10⁻⁶ A/cm² have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr₂O₃ surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.     

Influence of gate oxide breakdown on MOSFET device operation

The degradation of MOS transistor operation due to soft breakdown and thermal breakdown of the gate oxide was studied. Important transistor parameters were monitored during homogeneous stress at elevated temperature until a breakdown event occurred. In case of NMOSFETs the only noticeable signature of soft breakdown is an increase in off current due to enhanced gate induced drain leakage current (GIDL). A model is proposed and it is concluded that this effect only arises if the soft breakdown is located within the gate-to-drain overlap region. The influence of soft breakdown on PMOSFETs is discussed based on the model of enhanced GIDL for NMOSFETs. The degradation due to thermal breakdown of the gate oxide was investigated in detail. As a conclusion, a careful selection of device parameters is necessary in order to detect a device breakdown caused by thermal gate oxide breakdown.     

Edge hole direct tunneling leakage in ultrathin gate oxidep-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p⁺ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T_OX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E_OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E_OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected     

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.     

Resistive gate DMOST for low distortion mixing

A new device for mixing in the VHF range is presented which has very low third-order distortion. The device consists of a DMOST having a polysilicon resistive gate which is biased by a d.c. current that flows at right angles to the source to drain current in the DMOST. As a result of this gate bias current the device has a drain current to input gate voltage characteristic with a large square low region when the drain operates above the “pinch off” voltage. Samples of the device exhibit an extremely quadratic behaviour over several volts of the input gate voltage.     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs     

Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET

This paper present, the modeling and estimation of edge direct tunneling current of metal gate (Hf/AlN_x) symmetric double gate MOSFET with an intrinsic silicon channel. To model this leakage current, we use the surface potential model obtained from 2D analytical potential model for double gate MOSFET. The surface potential model is used to evaluate the electric field across the insulator layer hence edge direct tunneling current. Further, we have modeled and estimated the edge direct tunneling leakage current for high-k dielectric. In this paper, from our analysis, it is found that dual metal gate (Hf/AlN_x) material offer the optimum leakage currents and improve the performance of the device. This feature of the device can be utilized in low power and high performance circuits and systems.     

Composite TiSi2/n + poly-Si low-resistivity gate electrode and interconnect for VLSI device technology

A composite polycide structure consisting of refractory metal silicide film on top of polysilicon has been considered as a replacement for polysilicon as a gate electrode and interconnect line in MOSFET integrated circuits. This paper presents fine-line patterning techniques and device characteristics of MOSFET's with a TiSi2polycide gate. A coevaporated TiSi2polycide gate was chosen for this study because it had 2 to 5 times lower resistivity as compared to other silicides. Polycide formation by electron-beam coevaporation is chosen in preference to sputtered TiSi2because of lower oxygen contamination. The coevaporation technique to form TiSi2polycide with a sheet resistivity of 1 Ω/square (bulk resistivity of 21 µΩ.cm) is described. Anisotropic etching of nominally 1-µm lines with a 15:1 etch selectivity against oxide is reported. Measurements of metal-semiconductor work function, fixed oxide charge density, dielectric strength, oxide defect density, mobile-ion contamination, threshold voltage, and mobility have been made on polycide structures with 25-nm gate oxides. These MOS parameters correspond very closely to those obtained for n+ poly-Si gates. In addition, the specific contact resistivity between Al and TiSi2polycide is lower than the contact resistivity between Al and polysilicon by one order of magnitude.     

MOS characteristics of substituted Al gate on high-/spl kappa/ dielectric

Substituted aluminum (SA) metal gate on high-/spl kappa/ gate dielectric is successfully demonstrated. Full substitution of polysilicon with Al is achieved for a Ti-Al-polysilicon-HfAlON gate structure by a low-temperature annealing at 450/spl deg/C. The SA gate on HfAlON dielectric shows a very low work function of 4.25eV, which is well suitable for bulk nMOSFETs. The SA process is fully free from the Fermi-level pinning problem. In addition, the SA process also shows improved uniformity in leakage current distribution compared to fully silicided metal gate.     

Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well