Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing

A new method for the testing of combinational digital circuits is presented. The method is based on the concept of the ‘index vector’ of a switching function (Gupta 1987), and represents an extension of syndrome testing. A large percentage of syndrome untestable faults are found to be index vector testable. An approach to testing index vector untestable circuits that relies only on the function realized by the circuit and is independent of the circuit topology is presented. The method can be used for the detection of both single and multiple stuck-at faults in a combinational circuit.     

CMOS电路开关级测试生成的一种新算法

本文提出了一种新的CMOS电路开关级测试生成算法,该算法以Hayes模型为基础,以开关级代数为工具,充分利用CMOS电路自身的特点,生成CMOS电路的完全测试集,这种算法较之于已有的算法简单而有效,检测CMOS电路的常开型故障需一对测试码,本文给出了一种简单的求一对稳健测试码的方法,基于这种算法,我们开发了一个测试自动生成软件。     

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.     

Testable design of two-dimensional cellular logic arrays for detecting stuck-at and bridging faults

In this paper the problem of detecting bridging faults in two-dimensional (2-D) cellular logic arrays realizing an arbitrary Boolean function is considered in a new framework. A testable design of such combinational logic arrays has been proposed in which a set of universal tests can be initiated to detect all single stuck-at and bridging faults. The augmentation of the network for inducing testability is simple and is also independent of the function realized.     

Recent Developments in the Theory and Practice of Testable Logic Design*

This paper surveys and summarizes the major contributions to the theory and practice of testable logic design. The first part, dealing with the theoretical procedures, discusses the design of easily testable combinational, sequential, and iterative networks, illustrating major techniques with common running examples. The second part comments on the more practical aspects such as board layout, test point siting, and other facilities for easing the problems associated with testing.     

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

考虑逻辑门延时的冗余固定故障检测方法

提出利用瞬态电流测试(IDDT Testing)方法检测数字电路中的冗余固定故障。检测时采用双向量模式,充分考虑逻辑门的延时特性。针对两类不同的冗余固定故障,分别给出了激活故障的算法,在此基础上再对故障效应进行传播。SPICE模拟实验结果表明,该方法能有效地区分正常电路与存在冗余故障的电路,可以作为电压测试方法的一种有益的补充。     

IDDT: Fundamentals and Test Generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.     

CMOS电路瞬态电流测试方法研究

集成电路设计与测试是当今计算机技术研究的主要问题之一。集成电路测试技术是生产高性能集成电路和提高集成电路成品率的关键。基于固定型故障模型的测试方法已不能满足高性能集成电路,尤其是对CMOS电路的测试要求。CMOS电路的瞬态电流(IDDT)测试方法自80年代提出以来,已被工业界采用,作为高可靠芯片的测试手段。     

Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.     

Design and analysis of area efficient QCA based reversible logic gates

The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.     

Modeling Combinational Circuits Using Linear Word-level Structures

In many applications of circuit design and synthesis, it is natural and in some instances essential to manipulate logic functions and model circuits using word-level representations and arithmetic operations in contrast to bit-level representations and logic operations. This paper reviews linear word-level structures and formulates their properties for combinational circuit modeling. The paper addresses the following problem: given a library of gates with their corresponding word-level representations such as linear arithmetic expressions or respective graph structures, find a word-level model of an arbitrary combinational circuit/netlist using that library of gates and minimizing memory allocation and time delay requirements. We present a comprehensive study on linearization assuming various circuit processing strategies. In particular, we develop a new approach to manipulate linear word-level representations by means of cascades. The practical applicability of linear structures and developed algorithms is strengthen by considering the problem of timing analysis. All this is supported by the experimental study on benchmark circuits.     

Complete test-set generation for bridging faults in combinational-logic circuits

The present paper describes some algorithms for generating complete test sets for bridging faults in combinational logic circuits. It is shown how the concept of Boolean difference, which is well understood in the case of stuck-type fault situations, can be employed to generate the complete test set for bridging faults in combinational networks. The cases of single bridging fault and multiple input bridging fault are dealt with. An algorithm is also described for generating the complete test set of a combinational logic circuit in which a single stuck-type fault occurs in the presence of a bridging fault.     

Modeling and Testing for Timing Faults in Synchronous Sequential Circuits

Even with proper design, integrated circuits and systems can have timing problems because of physical faults or variation of parameters. The authors introduce a fault model that takes into account timing related failures in both the combinational logic and the storage elements. Using their fault model and the system's requirements for proper operation, the authors propose ways to handle flipflop-to-flipflop delay, path selection, initialization, error propagation, race-around, and anomalous behavior. They discuss the advantages of scan designs like LSSD and the effectiveness of random delay testing.     

基于多目标自适应遗传算法的逻辑电路门级进化方法

提出一种改进的遗传算法，通过网表级编码、多目标评估和遗传参数自适应等措施，可依据多个设计目标，以较少的运算量自动生成和优化逻辑电路．在数字乘法器、偶校验器等进化设计实验中，通过比手工设计和同类方法更优的新奇设计结果展示了该方法的有效性和先进性．     

Demand-driven logic simulation using a network of loosely coupled processors

Logic simulation is used extensively in the design of digital systems for the purpose of studying the behaviour of circuits under various conditions and for verifying the required performance of circuits. There is considerable interest in methods which reduce the simulation time during the design process. In this paper, we investigate how this can be achieved by simulating the action of logic circuits using a network of loosely coupled processors. Circuits modelled as directed graphs comprising clocked sequential components and (unclocked) arbitrary combinational logic gates can be partitioned into separate tasks each consisting of a sequential component with an associated network of combinational components. We present cost functions for evaluating a task subject to probabilistic assumptions about the functioning of the circuits. The circuit evaluation method used in the simulation process is significant. We apply lazy evaluation, a demand-driven evaluation strategy in which signals in the circuit are evaluated on a ‘need to do' basis, resulting in a considerable saving in circuit simulation time. We achieve distributed logic simulation using a network of workstations and show from experimental results that by using such a configuration, we essentially obtain a single computation engine which can be used to obtain speedups in circuit simulation when compared with uniprocessor simulation systems. Interprocess communications between tasks on different workstations proceed via remote procedure calls while local communications between tasks take place via shared memory. The method of partitioning used in the circuit model ensures that communications between tasks take place only at defined times in the simulation sequence.     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

AVS和MPEG-2熵解码结构与电路实现

针对高清视频AVS和MPEG2解码系统,提出一种新的可复用的熵解码电路。该电路采用复用的结构,每个周期内完成一个AVS/MPEG2码字的解码;采用组合逻辑映射查表技术,不需要存储AVS码表;通过复用解码控制电路,减小了面积。对该模块进行了仿真和综合,在0.18微米工艺下,频率为166 MHz,面积为9k等效逻辑门,存储器使用量为3 kbit ROM。