New experimental evidence for minority-carrier reflection at negative-barrier MIS contacts

Recently, measurements of the open-circuit voltage of solar cells with negative-barrier metal-insulator-semiconductor (MIS) back contacts have been used to demonstrate that such contacts can function as the electrical analogues of metallurgical high-low junctions. In this brief, further experimental evidence for the minority-carrier reflecting properties of the negative-barrier MIS junction is presented. First, it is shown that a negative-barrier Mg-SiOx-nSi back contact can be used to enhance the long-wavelength photoresponse of p⁺-n solar cells in the same manner as a diffused n⁺back-surface field. Secondly, measurements of the effective surface-recombination velocity for an Mg-SiOx-nSi contact and for a diffused n-n⁺high-low junction formed on an identical substrate are reported. Both junctions gave very low values of recombination velocity, on the order of 50 cm/s.     

Effect of emitter contact on current gain of silicon bipolar devices

The common-emitter current gain β of silicon n-p-n bipolar transistors with shallow (200 nm) emitters contacted by either i) Al, ii) Pd2Si + Al, or iii) n⁺polysilicon + Al are compared. For the same base doping profile, β(Al) is typically about 25 percent larger than β(Pd2Si), while β(poly) is typically several times larger than β(Pd2Si). The dependence of the base current on temperature and on the thickness of the polysilicon layer indicates that the base current is not determined by the silicon-polysilicon interface properties, such as tunneling through an interfacial oxide layer, but by the transport of holes in the n⁺polysilicon layer. A simple two-region (n⁺silicon region and n⁺polysilicon region) model is presented which satisfactorily explains the experimental results in terms of lower hole mobility in the n⁺polysilicon than in the monocrystalline n⁺silicon.     

Recombination measurement of n-type heavily doped layer in high/lowsilicon junctions

The hole lifetime within a heavily doped n⁺ region has been determined using a measurement technique which evaluates the effective recombination velocity of n-n⁺ interfaces. The recombination model of a high/low junction is reviewed. The experiment is described. The measurement results are presented and discussed. Measurements of n⁺ layers of different types, like substrates, implanted buried layers, and diffused layers, suggest that the minority-carrier lifetime of such regions can be strongly degraded by the device fabrication processes. Results are consistent with the Shockley-Reed-Hall (SRH) lifetime value, which is two orders of magnitude lower than previously published values for bulk material     

Modeling of minority-carrier surface recombination velocity atlow-high junction of an n+-p-p+ silicon diode

Modeling of recombination velocity of minority carriers at the p-p ⁺ low-high junction end of the p-base region of n⁺-p-p⁺ silicon diodes is carried out by taking the minority-carrier recombination effects in the space-charge region (SCR) of the low-high (L-H) junction into account. Solving Poisson's equation in the SCR numerically revealed that the SCR is composed of an accumulation layer on the p side and a depletion layer on the p⁺ side. Generally, the depletion layer is very thin as compared with the accumulation layer, and the built-in potential across the depletion layer never exceeds the thermal voltage, i.e. kT/q. Further, the minority-carrier recombination in this layer is also insignificant. For most L-H junction-based silicon devices, in practice, the minority-carrier recombination in the accumulation layer controls the value of the effective minority-carrier recombination velocity (S_eff) at the back surface of the p-base region and the influence of the recombination in the heavily doped p⁺ region is less significant     

Determination of minority-carrier lifetimes of bipolar transistors from low-current hFEfall-off

The minority-carrier lifetimes τn0and τp0of bipolar transistors are determined from low-cufrent hFEfall-off. The relative magnitude of surface space-charge-layer recombination current is taken into account. This method is particularly attractive in achieving accurate computer models of bipolar transistors suitable for network analysis and design.     

An approach toward 25-percent efficient GaAs heteroface solar cells

To approach one-sun 25% efficiency in GaAs solar cells, it is necessary to improve the basic understanding of internal loss mechanisms by a combination of characterization techniques and computer models. A methodology is developed to measure and evaluate minority-carrier transport properties such as lifetime and recombination velocity throughout the device structure in a 21.2% GaAs cell. It is found that this cell has a recombination velocity of 1.25×10⁵ cm/s at the AlGaAs/GaAs interface and a base minority-carrier lifetime of 8 ns. Guidelines are provided to increase the efficiency of this cell to 24% with slightly increased surface passivation and base lifetime using effective recombination velocity and device modeling computer programs. Further device modeling is performed to show that efficiencies of 25% can be obtained using a modified heteroface structure with a moderate surface recombination and their relation to device design are fully understood     

A study of n+-SIPOS:p-Si heterojunction emitters

We have found experimental conditions for the growth of n⁺-SIPOS:p-Si heterojunction emitters with forward saturation current J0= 10^-14Amps/cm²or equivalently "emitter Gummel number" Ge= 3.3 × 10¹⁵s/cm⁴. This outstanding figure of merit seems to rely upon the presence of a thin interfacial oxide between the SIPOS and the crystalline silicon. We invoke a model in which majority-carrier (electron) contact is made by microcrystalline grains which protrude into the interfacial oxide but minority-carrier (hole) recombination is inhibited by the small fractional area coverage of such contacts. The result is an emitter structure which is robust and relatively insensitive to variations in processing conditions.     

Characterization of thermally oxidized n+polycrystalline silicon

The properties of thermally grown silicon dioxide films on n⁺polysilicon are studied using cross-sectional TEM, and electrical measurements to evaluate conduction, electron trapping, destructive breakdown and wearout mechanisms. All of the above electrical parameters are found to be degraded by any increase in the degree of surface roughness at the oxide-polysilicon interface. Our results suggest that a significant improvement in the insulating properties of the SiO2films can be achieved if the polysilicon is initially deposited in the amorphous phase at 560°C rather than the polycrystalline phase at 620°C. For example, for dry-oxidized diffusion-doped films, there is an increase in oxide breakdown field from 3.0 MV . cm^-1to 6.2 MV . cm^-1, and a reduction in leakage (Fowler-Nordheim) current of two orders of magnitude. Furthermore, it is shown that the long-term reliability of n⁺polysilicon/SiO2/n⁺polysilicon structures is directly related to the degree of interface texture; i.e., a smoother interface will result in a significant reduction in electrical wearout and an increase in time to failure.     

The effect of reflecting contacts on high-field transport

The effect of reflecting contacts on high-field transport is investigated by detailed Monte Carlo simulations of electron transport in an n^-GaAs region that terminates in an n⁺GaAs/metal contact. We determine that the average electron velocity in the n^-region of the device decreases rapidly (because of reflections at the contact) as the doping concentration in the n⁺contact region decreases. We study the n⁺concentration range of 2 × 10¹⁸cm^-3to 1 × 10¹⁹cm^-3The probability of reflection at the contact is found to depend sensitively on the energy and momentum of the electrons impinging on the contact region as long as transport at the contact is dominantly by tunneling. The dependence is weaker for transport through the contact by thermionic emission. The velocity degradation due to electrons reflected at the contact is less severe for high electric fields with the electrons transferred to the upper valleys.     

Complementary MOS—Bipolar transistor structure

Bipolar transistors can be used to increase the driving capabilities of complementary MOS transistors while retaining the low power dissipation feature. The fabrication of n-p-n bipolar transistors is compatible with the fabrication of the complementary MOS transistors in a monolithic structure. Common collector n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter, a diffused p^-isolation region as base and an n^-substrate as collector with a hfegreater than 100. Lateral n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter and collector, and p^-isolation region as base with a hfegreater than 10.     

On the transport theory of Schottky barriers to polycrystalline silicon thin films

A theoretical investigation of electronic transport in metal contacts to polycrystalline silicon thin films is presented. Calculations based upon the reported values of grain-boundary potentials indicate that the thermionic emission theory may be applied to the majority-carrier transport only for low bias voltages. At larger bias voltages, one needs to take account of the voltage lost to the space-charge regions adjacent to the grain boundaries, and a transition from electrode-limited to bulk-limited majority-carrier transport results. We further demonstrate that the injection of minority carriers can dominate the dark current for a range of grain size and interface state densities at the grain boundaries. Under these conditions, the current obeys anexp (qV/2kT)dependence reminiscent of space-charge recombination, although the origin of the current in this case is minority-carrier diffusion current, with recombination only at grain boundaries in the neutral region. This is a special case of the "high-injection" regime observed in single crystals, but in the present situation it is found even for low bias voltages as a consequence of the band bending at the grain boundaries, which makes the material nearly intrinsic at these points. Finally, we show that the effective minority-carrier diffusion length for the injected carriers under dark conditions itself increases with bias voltageVapproximately asexp (qV/2kT), in striking contrast to previous treatments.     

Mapping of electrical leakage in transistors by anodic oxidation

Recently developed electrochemical methods permit the optical mapping of large and small bipolar transistors in an integrated circuit for electrical leakage before metallization. In one methods the emitters of the leaky transistors are decorated by a deposit of amorphous silicon produced as a result of anodic dissolution of the n⁺silicon in that region. Other methods depend on the colors of the anodic oxide grown on the emitter and base regions of the leaky transistors. A close relationship has been established between the oxide growth on the emitter and the base regions and the defective electrical characteristics of the transistor.     

Effects of buried layer geometry on characteristics of doublepolysilicon bipolar transistors

Dependences of electrical characteristics of double polysilicon transistors on n⁺ buried islands (subcollector) are examined. By simply modifying layouts of the buried island, the Early voltage (V _A), collector-to-emitter breakdown voltage (BV_CEO), and β×V_A product of transistors are increased from 42, 5.6, and 3070 V to 61, 6.7, and 3820 V, respectively, while the peak cutoff frequency at a V_CE of 1.5 V is decreased from around 21 to 17 GHz. Exploiting these results, it may be feasible to inexpensively integrate transistors with better f _T-BV_CEO and f_T-V_A tradeoffs for analog and power handling characteristics along with transistors optimized for high-speed operation. These results also indicate that the buried island geometry control could be an issue for controlling electrical characteristics for scaled bipolar transistors     

InP/InGaAs HBTs with n+-InP contacting layers grown byMOMBE using SiBr4

InP/InGaAs heterojunction bipolar transistors (HBTs) with low resistance, nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers have been demonstrated with excellent DC characteristics. A specific contact resistance of 5.42×10^-8 Ω·cm², which, to the best of our knowledge, is the lowest reported for TiPtAu on n-InP, has been measured on InP doped n=6.0×10¹⁹ cm^-3 using SiBr₄. This low contact resistance makes TiPtAu contacts on n-InP viable for InP/InGaAs HBTs     

The Hooge parameters of n+-p-n and p+-n-p silicon bipolar transistors

We establish here again the fact that the Hooge parameters of NEC57807 n⁺-p-n and in GE82 p⁺-n-p silicon bipolar transistors are orders of magnitude smaller than the value 2 × 10^-3postulated earlier. In the NEC57807 devices neither the base 1/fnoise nor the collector 1/fnoise is of the diffusion-fluctuation type. In the GE82 devices the collector 1/fnoise is not of the diffusion-fluctuation type, but the base 1/fnoise is of that type. We have given, also, a theory of the effects of surface recombination fluctuations in the emitter-base space-charge region on the base noise and the collector noise and find a noise spectrum that varies asI_gammawhere 0.5 < γ < 1.6 when going from small to large currents.     

Analysis of minority-carrier transport in polysilicon devices

Key assumptions are made, with justification, to simplify the three-dimensional, nonlinear boundary-value problem that defines minority-carrier transport, including recombination, in polysilicon devices. These assumptions enable the separation of the grain-boundary recombination analysis, which is based on quasi-equilibrium in the space-charge region, from the intragrain transport analysis, which is done by partitioning the grain into subregions in which the minority-carrier flow is predominantly one-dimensional. The analyses are coupled through the effective minority-carrier recombination velocity at the grain boundary, which generally is dependent on the minority-carrier density in the quasi-neutral grain. Limitations of the model implied by the quasi-equilibrium assumption are effectively removed by recognizing that when conditions obtain that negate quasi-equilibrium, the effective recombination velocity is fixed at the minority-carrier kinetic-limit velocity. The model development is facilitated by computer-aided numerical analysis of the grain-boundary recombination and is supported by qualitative discussion of the underlying physics.     

Spectral response limitation mechanisms of a shallow junction n+-p photodiode

Modulated monochromatic visible light at various wavelengths was used to generate photocurrent in a silicon n⁺-p diffused diode. A numerical model which includes electric field, heavy doping bandgap reduction, and doping level mobility dependence was used with fitting techniques to determine the carrier lifetime in the n⁺-region at each wavelength. From these measurements it was concluded that the physical mechanisms involved in limiting the spectral response of the n⁺-p photodiode at short wavelengths (0.42 µm) is due to heavy recombination of photogenerated carriers in the n⁺-region. The latter is caused by the heavy doping which results in a fraction of a nanosecond minority carrier lifetime and a retarding or reduced electric field in the n⁺-region. Surface recombination velocity has little influence on this loss mechanism.     

Impact of fluorine incorporation in the polysilicon emitter of NPNbipolar transistors

We demonstrate that fluorine incorporation in the polysilicon emitter of NPN bipolar transistors significantly reduces the current gain h_fe. The gain degradation can be related to a reduction of the barrier to hole transport at the poly-Si/mono-Si interface. In addition to a gain reduction, fluorinated-emitter transistors display lower base recombination currents (at low base-emitter biases) than nonfluorinated emitter devices, suggesting that fluorine passivates recombination centers in the emitter-base space charge region     

A low-voltage high-speed silicon photodiode with buried isolation region for short-haul optical-fiber communications

A new epitaxial silicon p-i-n photodiode has been developed for short-haul optical-fiber communications that can be operated at biases as low as 4 V. The device has a heavily doped 5-µm-thick p⁺⁺isolation-region between the p⁺substrate and the π-epitaxial layer. Fast rise and fall times (2 ns), and low leakage current (40 pA) result from the recombination and trapping of the minority-carrier electrons in the substrate. Experimental results on such an n⁺-π-p⁺⁺-p⁺device with 1.1-mm²photosensitive area and 25-µm epi-layer thickness show quantum efficiency of 80 percent at 825-nm wavelength.     

High-current-gain submicrometer InGaAs/InP heterostructure bipolartransistors

Common-emitter current gains of 115 and 170 are achieved in transistors with emitter dimensions as small as 0.3×3 and 0.8×3 μm², respectively. These results are comparable with scaling experiments reported for Si bipolar devices and represent a significant improvement over AlGaAs/GaAs heterostructure bipolar transistors. Both the low surface recombination velocity and nonequilibrium carrier transport in the thin (800-Å) InGaAs base enhance the DC performance of these transistors