Direct digital process control: Practice and algorithms for microprocessor application

Process control applications and control algorithms suited for microprocessors are surveyed. Applications are noted both in large, general purpose process control systems and in specialized applications that have been made possible by the availability of computing power in small packages. Distributed control and use of extended data buses (data highways), both made possible by extensive use of microprocessors, are becoming standard in general purpose systems. General purpose process control systems still utilize proportional-integral-derivative (PID) algorithms and variants of them for the most part. Some recent research results on algorithms designed for use in stand-alone, single-loop calculator or microprocessor-based controllers are presented. These algorithms, which could also be used in direct digital control (DDC) systems, are specifically tailored for simple implementation in a relatively low computing power, discrete-time environment.     

Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation

The Intellectual Property (IP)-based design for high-throughput dedicated digital signal processing (DSP) systems is obviously an important issue for improving not only design productivity, but also design from the high level of abstraction. However, in some cases, synthesizable register transfer level (RTL) model obtained by an automatic assembly of RTL IPs can be wrong due to delays induced by implementation constraints. In this paper, we present the formalization of the problem and propose an approach called automatic delay correction method (ADCM) to solve the problem without inserting an extra interface circuitry. The approach automatically inserts control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IPs. The delays may be managed by registers or by counters included in the control structure. A formal theory of ADCM is developed to guide the implementation and guarantee optimal solutions in latency and area. Through experiments with synthetic example and three real world high-throughput DSP circuits, we also show the effectiveness of our approach.     

On the efficiency of image and video processing programs on instruction level parallel processors

While in the last decade image and video processing (IVP) have gradually moved from special purpose computer architectures based on massive parallelism (MP) to general purpose computer architectures based on instruction-level parallelism (ILP), a new challenge is now to be faced by the IVP community, namely the application of IVP also in small-size embedded systems (e.g., video players, smart cameras, digital diaries, etc.) based on ILP processors. Because of the requirements of low size, weight, and power consumption, these embedded systems do not take advantage of processors that feature advanced dynamic code optimization mechanisms such as those based on instruction reordering and register renaming. On the other hand, the compile time techniques of present generation compilers do not appear to be aggressive enough to exploit the massive parallelism of IVP tasks in ILP architectures, thus leading to inefficient programs. This paper analyzes the efficiency of IVP programs on ILP CPUs. In particular it presents: (1) a reference model for the efficient design and implementation of highly parallel programs, such as the ones of the IVP domain; (2) an analysis of the inefficiencies of IVP programs implemented on ILP processors; and (3) a set of techniques, deriving from the reference model, that overcome these inefficiencies. These techniques are based on a novel computing paradigm called bucket processing.     

Multilevel barrel shifter for CORDIC design

The coordinate rotation digital computer (CORDIC) algorithm is used in numerous special purpose systems for real-time signal processing applications. It uses barrel shifters to complete shift operations. However, the barrel shifter occupies most of the area of the CORDIC chip. A new structure of multilevel barrel shifters is presented. With this structure the shifter size is reduced by 68%. The novel structure can also slightly reduce the latency time of shift operations     

行波管自动测试设备控制与保护系统

介绍了一种行波管自动测试设备控制与保护系统,系统采用工业控制计算机(简称工控机)作为主控平台,单片机电路作为实时控制与保护下位机,提供行波管高压电源所需的电压基准和调制器所需的定时信号,实现电路各项数据的采样保护.工控机软件采用Visual Basic语言编程,下位机软件采用C语言编程,软件结构模块化设计,通过友好的操作界面对行波管进行自动测试.     

Computer architecture for signal processing

There is an increasing trend to use digital signal-processing techniques to solve real-time problems. This leads to a need for processors which can perform complicated signal-processing algorithms on large amounts of data at high speeds. Computer architectures for this purpose ate shown to arise from a consideration of several structural factors, including technology, the algorithms to be performed, data structures, and the programming language. When these factors are complementary, efficient yet economical designs result. The structural factors are described, and then several computer designs are discussed in light of this conceptual framework.     

基于DSP+CPLD的网络数据传输系统设计

介绍了基于DSP+CPLD和以太网卡的网络数据传输系统设计方案。设计了以DSP芯片TMS320VC5509A、CPLD芯片EPM3128A和网络接口控制器RTL8019AS为核心的网络接口电路;在DSP的结构中精简并实现了TCP/IP协议;通过编写C语言程序设计了系统与PC机进行网络数据传输的主程序,最后实现了数据的传输。实验证明:以DSP+CPLD和RTL8019AS网络芯片构成的网络数据传输系统,能与PC机进行数据传输,且工作稳定可靠。     

An undergraduate computer engineering option for electrical engineering

Computer engineering is concerned with the organization, design, and utilization of digital processing systems. These may be general purpose computers or more specialized digital systems that are concerned with communications, control, information processing, etc. The rapidly expanding application areas for digital processing techniques require increasing numbers of properly trained engineers, and it is the responsibility of electrical engineering education to provide the necessary educational opportunities. A means for doing this is an undergraduate computer engineering option within electrical engineering. The curriculum for such an educational program would be both hardware and software oriented, as described.     

Time-sharing bibliography

The bibliography includes articles dealing with the simultaneous independent shared use of computers. Real time, on-line, memory or facility allocation, multi-programming, and multi-processing terminology is evolved. Though a number of computer applications are reported, the requirements of special or dedicated time-sharing systems seem to be within the capability of most of the general-purpose time-sharing systems which are beginning to emerge. The systems are being designed for 100 percent availability, memory and facility allocation among users, a common file or data base, and direct access by the users via consoles (for example, typewriter, display, etc.).     

一种基于DSP的数据以太网传输系统

为了满足高速信号处理要求,本文设计和实现一种基于DSP的高速数据以太网传输及处理系统,能够实现超过1M字的采样,并实时通过以太网传输给上位机.通过32位150M快速DSP(TMS320F2812)控制CPLD(EMP240)驱动10M的RTL8019AS网络芯片,实现了DSP和上位机的以太网数据传输,速度超过1M.利用数字信号处理器DSP和RTL8019AS实现了以太网数据的实时传输,完成了以TMS320F2812为核心处理系统与以太网连接的硬件接口.应用此硬件平台实现了嵌入式TCP/IP协议,完成了通过以太网和机之间传输数据.     

无线射频基础创新实验中数传电路设计

无线射频基础实验系列致力于本科生创新意识和创新能力培养。此实验系列通过MODEM模块和数字接口可实现数字通信。若配合各种传感器和计算机控制,可构成多种无线监控系统。该系统具有稳定可靠、经济可行等特点。     

An Overview of a Compiler for Mapping Software Binaries to Hardware

As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (FPGAs) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C 6211 DSP (VLIW) and the ARM 922 T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix FPGAs. We record overall performance gains of 1.5-26.9 for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.     

A Programming Discipline for Laboratory Computing

The history of the development of digital computer systems for use in medical care and biological laboratory experiments is reviewed, with special emphasis on programming languages. The relevance to this application of techniques first used in the design of operating systems for simultaneous multiple use of large computer systems and in performing concurrent real-time tasks is demonstrated. A number of applications and specially designed computerized instruments for neurophysiology, in which the programming language Modula was used, are described. The strengths and limitations of Modula are evaluated. The essential parallelism of laboratory and clinical monitoring tasks would seem to promote the use of the emerging technology of multitasking and multiprocessor languages and systems.     

Finite Buffer Behavior with Poisson Arrivals and Random Server Interruptions

A queueing model with finite buffer size, Poisson arrival process, synchronous transmission and server interruptions is studied through a Bernoulli sequence of independent random variables. An integrated digital voice-data system with Synchronous Time-Division Multiplexing (STDM) for voice sources and Poisson arrival process for data messages is considered as an application for this model. The relationships among overflow probabilities, buffer size and expected queueing delay due to buffering for various traffic intensities are obtained. The results of this study are portrayed on graphs and may be used as guide lines for the buffer design in digital voice-data systems. Although this study arose in the design of a buffer for digital voice-data systems, the queueing model developed is quite general and may be useful for other industrial applications.     

Transaction-level power analysis of VLSI digital systems

The increasing complexity of VLSI digital systems has dramatically supported system-level representations in modeling and design activities. This evolution makes often necessary a compliant rearrangement of the modalities followed in validation and analysis tasks, as in the case of power performances estimation.Nowadays, transaction-level paradigms are having a wider and wider consideration in the research on electronic system-level design techniques. With regard to the available modeling resources, the most relevant framework is probably the transaction-level extension of the SystemC language (SystemC/TLM), which therefore represents the best platform for defining transaction-level design techniques.In this paper we present a macro-modeling power estimation methodology valid for SystemC/TLM prototypes and of general applicability. The present discussion illustrates the implementation modalities of the proposed approach, verifying its effectiveness through a comparison with RTL estimation techniques.     

The Khoros software development environment for image and signalprocessing

Data flow visual language systems allow users to graphically create a block diagram of their applications and interactively control input, output, and system variables. Khoros is an integrated software development environment for information processing and visualization. It is particularly attractive for image processing because of its rich collection of tools for image and digital signal processing. This paper presents a general overview of Khoros with emphasis on its image processing and DSP tools. Various examples are presented and the future direction of Khoros is discussed.     

Process control software

This paper examines the nature of the software which is necessary so that a real-time computer may be used to control industrial processes. The general nature of a process control software system is discussed, and several methods for implementing such a system are examined. This paper is divided into several sections. First, the general structure of process control software systems is examined, and the programming problems associated with developing such a system are discussed. Then several tools for doing this programming are discussed, including problem-oriented languages, "fill-in-the-blank programming systems," procedural programming languages, and the operating systems which are used to tie the different portions of a process control system together. This paper closes with a dicussion of future trends in process control software, and recent activities in developing software standards. It will be assumed that the reader is generally familiar with software with at least a passable knowledge of FORTRAN programming.     

数字电路的VHDL语言设计方法

分析了传统硬件电路设计的“自下而上”的方式和步骤，针对设计中存在的调试与试验相对滞后的问题，提出了采用“自上而下”的VHDL电路设计方法，按照硬件设计的三个层面，对行为级描述、寄存器传输级描述和逻辑综合进行了说明并给出了电路设计流程，通过SCI设计实例对该设计方法做了进一步的诠释和具体分析，为数字电路的VHDL语言设计提供了可借鉴的思路和方法．     

Elite: A Digital Dedicated Hardware System for Movement Analysis Via Real-Time TV Signal Processing

The system illustrated in this paper has been designed and developed particularly for automatic and reliable analysis of body movement in various conditions and environments. It is based on real-time processing of the TV images to recognize multiple passive markers and compute their coordinates. This performance is achieved by using a special algorithm allowing the recognition of markers only if their shape matches a predetermined "mask." The main feature of the system is a two-level processing architecture, the first of which includes a dedicated peripheral fast processor for shape recognition (FPSR), designed and implemented by using fast VLSI chips. The second level consists of a general purpose computer and provides the overall system with high flexibility. The main characteristics are: no restriction on the number of markers, resolution of one part in 2500, and a 50 Hz sampling rate independent of the number of markers detected. The prototype has been fully developed, and preliminary results obtained from the analysis of several movements are illustrated.