用阱作高阻漂移区的LDMOS导通电阻的解析模型

分析了一个用阱作为耐高压漂移区的LDMOS的导通电阻，提出了带有场极板的高阻漂移区导通电阻的计算公式，改进了双扩散沟道导通电阻的计算公式. 针对一个LDMOS的例子做了计算，并将其与相同参数情况下用MEDICI软件模拟的结果作了对比. 结果表明两者相差仅5%，这说明所得公式可用于该类型LDMOS的分析和设计.     

对异型硅岛实现的厚膜全耗尽SOIMOSFET的模拟研究

本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间.     

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5 μm, which is due to the rapid increase of the base transport factor (_T).     

The effects of glass-substrate’s surface-treatment on the characteristics of N-channel polycrystalline silicon thin film transistors

We have examined the performance and hot-carrier stress reliability of n-channel polycrystalline silicon (poly-Si) thin film transistors (TFTs) on RCA-leached glass. We have found out that the TFT’s performance and reliability are improved by RCA-leaching of the glass when compared to TFTs on bare glass due to the formation of a silica-rich layer on the glass surface by the RCA-leaching. The silica-rich layer acts as a barrier for impurity diffusion from glass as well as it modifies the poly-Si/glass interface which determines the physical structure of the active poly-Si.     

THE GROWTH OF MONOCRYSTALLINE SILICON THIN FILM ON INSULATOR (SOI) BY SCANNING ELECTRON BEAM

An experiment for preparation of SOI films by using the scanning electron beam to modify the polycrystalline silicon on SiO2 is presented. This method takes on the epitaxial lateral growth of liquid phase with the crystallon to form monocrystalline silicon films. The effects of the beam power density, scanning velocity, temperature of the substrates and the construction of samples on the quality of the monocrystalline silicon films were discussed. A good experimental result has been obtained, the monocrystalline silicon zone is nearly 200×25μm2.     

Amorphous silicon detector and thin film transistor technology for large-area imaging of X-rays

This paper reviews amorphous silicon imaging technology in terms of the detector operating principles, electrical and optoelectronic characteristics, and stability. Also, issues pertinent to thin film transistor stability are presented along with optimization of materials and processing conditions for reduced V_T-shift and leakage current. Selected results are shown for X-ray and optical detectors, thin film transistors, and integrated X-ray pixel structures. Extension of the current fabrication processes to low (120°C) temperature, enabling fabrication of thin film electronics on flexible (polymer) substrates, are also discussed along with preliminary results.     

多晶硅薄膜的新型激光晶体制备方法

采用两步激光晶化方法制备了多晶硅薄膜,其晶粒尺寸为１．１μｍ,比用传统单步晶化制备的薄膜晶粒尺寸大,表明该方法法对扩大晶粒尺寸很有效。拉曼光谱分析表明０．３０Ｊ／ｃｍ＾２晶化的薄膜结晶程度已很高。     

High-performance polycrystalline silicon thin-film transistor technology using low-temperature metal-induced unilateral crystallization

Low-temperature metal-induced unilaterally crystallized polycrystalline silicon thin-film transistors (TFTs) have been developed and characterized. These TFTs are better than their solid-phase crystallized counterparts in many process and device performance measures, such as shorter and simpler process flow, higher field-effect mobility, reduced leakage current, better immunity to early drain breakdown and much improved spatial uniformity of device parameters. They have been used to realize active matrices for liquid-crystal (LC) and organic light-emitting diode (OLED) flat-panel displays.     

多晶硅薄膜晶体管Kink效应研究与建模

多晶硅薄膜晶体管(P-Si TFTs)技术在SOP(system on panel)显示应用中发挥着越来越重要的作用.随着尺寸的不断缩小,P-si TFT 的Kink效应越来越明显,对有源液晶显示矩阵和驱动电路的性能影响很大.对发生Kink效应的物理机制、二雏数值仿真及其一维解析模型进行了分析,讨论了晶粒边界、沟道长度与Kink效应的关系,提出建立适合电路仿真的一维解析模型的关键与展望.     

多晶硅薄膜的新型激光晶化制备方法

采用两步激光晶化方法制备了多晶硅薄膜 ,其晶粒尺寸为 1.1μm,比用传统单步晶化制备的薄膜晶粒尺寸大 ,表明该方法对扩大晶粒尺寸很有效。拉曼光谱分析表明 0 .30 J/ cm2晶化的薄膜结晶程度已很高     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200 V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.     

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

Broadband light trapping with disordered photonic structures in thin‐film silicon solar cells

We theoretically investigate light trapping with disordered 1D photonic structures in thin‐film crystalline silicon solar cells. The disorder is modelled in a finite‐size supercell, which allows the use of rigorous coupled‐wave analysis to calculate the optical properties of the devices and the short‐circuit current density J_sc. The role of the Fourier transform of the photonic pattern in the light trapping is investigated, and the optimal correlation between size and position disorder is found. This result is used to optimize the disorder in a more effective way, using a single parameter. We find that a Gaussian disorder always enhances the device performance with respect to the best ordered configuration. To properly quantify this improvement, we calculate the Lambertian limit to the absorption enhancement for 1D photonic structures in crystalline silicon, following the previous work for the 2D case [M.A. Green, Progr. Photovolt: Res. Appl. 2002; 10 (4), pp. 235–241]. We find that disorder optimization can give a relevant contribution to approach this limit. Finally, we propose an optimal disordered 2D configuration and estimate the maximum short‐circuit current that can be achieved, potentially leading to efficiencies that are comparable with the values of other thin‐film solar cell technologies. Copyright © 2013 John Wiley & Sons, Ltd.     

High voltage amorphous silicon TFT for use in large area applications

Previous work in high voltage amorphous silicon (a-Si) TFTs (HVTFTs) using an n⁺ μC-Si ohmic contact layer demonstrated that the soft contact TFT (SCTFT) design was a requirement for high voltage operation. In this research, conventional and high voltage TFT designs including the SCTFT are presented using an n⁺ a-Si contact layer. TFT ON-current measurements and series resistance extractions show that the conventional TFT performs equally well, if not better, at low and high voltages in comparison to all of the HVTFTs fabricated. The results indicate that the conventional space-efficient TFT design with an n⁺ a-Si contact layer is realizable for high fill-factor, high voltage applications such as direct detection, large area X-ray imaging. Also, the process reliability and performance for both conventional and HVTFT arrays can be improved for large area applications by the inclusion of an additional a-SiN layer.     

快速退火BF+注入非晶硅薄膜的显微分析

将具有能量９２ｋｅ Ｖ、剂量１×１０１５／ｃｍ ２ 的 Ｂ Ｆ＋ 注入由 Ｐ Ｅ Ｃ Ｖ Ｄ 方法制备的ａ Ｓｉ∶ Ｈ 薄膜中,然后用功率为 ６０ Ｗ 、束斑直径 ０２ｃｍ 的 Ｃ Ｗ Ｃ Ｏ２ 激光器进行 １０ｓ 快速退火。再用扫描电子显微镜（ Ｓ Ｅ Ｍ）进行显微形貌观察。分析结果指出：由于 Ｂ Ｆ＋ 的注入,使ａ Ｓｉ∶ Ｈ 薄膜中产生了多重结构缺陷,其表面轮廓是类似矩形和方形的图形;发现退火中的晶化是从这些缺陷的棱边开始。最后对晶化过程和机理进行了讨论。     

Boron‐doped hydrogenated silicon carbide alloys containing silicon nanocrystallites for highly efficient nanocrystalline silicon thin‐film solar cells

Boron‐doped hydrogenated silicon carbide alloys containing silicon nanocrystallites (p‐nc‐SiC:H) were prepared using a plasma‐enhanced chemical vapor deposition system with a mixture of CH₄, SiH₄, B₂H₆ and H₂ gases. The influence of hydrogen dilution on the material properties of the p‐nc‐SiC:H films was investigated, and their roles as window layers in hydrogenated nanocrystalline silicon (nc‐Si:H) solar cells were examined. By increasing the R_H (H₂/SiH₄) ratio from 90 to 220, the Si―C bond density in the p‐nc‐SiC:H films increased from 5.20 × 10¹⁹ to 7.07 × 10¹⁹/cm³, resulting in a significant increase of the bandgap from 2.09 to 2.23 eV in comparison with the bandgap of 1.95 eV for p‐nc‐Si:H films. For the films deposited at a high R_H ratio, the Si nanocrystallites with a size of 3–15 nm were formed in the amorphous SiC:H matrix. The Si nanocrystallites played an important role in the enhancement of vertical charge transport in the p‐nc‐SiC:H films, which was verified by conductive atomic force microscopy measurements. When the p‐nc‐SiC:H films deposited at R_H = 220 were applied in the nc‐Si:H solar cells, a high conversion efficiency of 8.26% (V_oc = 0.53 V, J_sc = 23.98 mA/cm² and FF = 0.65) was obtained compared to 6.36% (V_oc = 0.44 V, J_sc = 21.90 mA/cm² and FF = 0.66) of the solar cells with reference p‐nc‐Si:H films. Further enhancement in the cell performance was achieved using p‐nc‐SiC:H bilayers consisting of highly doped upper layers and low‐level doped bottom layers, which led to the increased conversion efficiency of 9.03%. Copyright © 2015 John Wiley & Sons, Ltd.     

一种具有超强电荷积累效应的高优值超结SOI LDMOS

A novel silicon-on-insulator(SOI) super-junction(SJ) LDMOS with an ultra-strong charge accumulation effect is proposed. It has two key features: an assisted-accumulation trench-type extending gate(TEG) with a high-k(HK) dielectric and a step-dopedN pillar(TEG-SD SJ LDMOS). In the on-state, electrons accumulate at the sidewall of the HK dielectric from the source to the drain by the TEG. Furthermore, the high permittivity of the HK dielectric leads to an ultra-strong charge accumulation effect. As a result, an ultra-low resistance current path is formed. The specific on-resistance(Ron;sp/ is thus greatly reduced and is independent of the drift doping concentration. In the off-state, the step-dopedN pillar effectively suppresses the substrate-assisted depletion effect by charge compensation. Moreover, the reshape effect of the HK dielectric and the new electric field(E-field) peak introduced by the step-dopedN pillar enhance the drift region E-field. Hence, the BV is improved. Simulation indicates that the TEG-SD SJ LDMOS achieves an extremely low Ron;sp of 1.06 m cm2 and a BV of 217 V. Compared with the conventional SJ LDMOS, the TEG-SD SJ LDMOS decreases the Ron;sp by 77.5% and increases the BV by 33%,exhibiting a high figure of merits(FOM=BV2/Ron;sp/ of 44 MW/cm2.