高压VDMOS的一种高精度静态物理模型

提出了高压VDMOS的一种高精度静态物理模型(HASPM)。在该模型中,基于更为合理 的假设而使得用解析方法求得了双扩散沟道区中的电场和电压;通过深入研究VDMOS 内部的物理特性,给出了一个关于漂移区电场的微分方程,并在整个漂移区都用解 析方法求解了该微分方程,由此求得了漂移区的电压降。计算结果表明, 该模型在漏端电流接近饱和处的稳定性有较大提高,具有较高的 计算精度,特别是在栅电压与漏电压都比较大的情况下,其计算精度有较大程度的提高。     

A majority-logic nanodevice using a balanced pair of single-electron boxes

This paper describes a majority-logic gate device that will be useful in developing single-electron integrated circuits. The gate device consists of two identical single-electron boxes combined to form a balanced pair. It accepts three inputs and produces a majority-logic output by using imbalances caused by the input signals; it produces a 1 output if two or three inputs are 1, and a 0 output if two or three inputs are 0. We combine these gate devices into two subsystems, a shift register and an adder, and demonstrate their operation by computer simulation. We also propose a method of fabricating the unit element of the gate device, a minute dot with four coupling arms. We demonstrate by experiments that it is possible to arrange these unit elements on a GaAs substrate, in a self-organizing manner, by means of a process technology that is based on selective-area metalorganic vapor-phase epitaxy.     

Quantum mechanical device modeling: FinFET having an isolated n+/p+ gate region strapped with poly-silicon

In this paper, we present our numerical study on FinFET having an isolated n+/p+ gate region strapped with metal and poly-silicon structure. Our theoretical work is based on 2-D quantum-mechanical simulator with a self-consistent solution of Poisson-Schr?dinger equation. Our numerical simulation revealed that the threshold voltage (VT) is controlled within -0.1 approximately +0.2 V with varying the doping concentration of the n+ and p+ polysilicon gate region from 1.0 x 10(17) to 1.0 x 10(18) cm(-3). We also confirmed that the better VT tolerance of the FinFET on the variation of the fin thickness can be expected over the conventional FinFET structure. For instance, the VT of the FinFET under this work exhibited 0.02 V tolerance with respect to the variation of the fin thickness change of 5 nm (from 30 to 35 nm) while the traditional FinFET demonstrates the tolerance of 0.12 V for the same variation of the fin thickness.     

一种基于压力泊松方程的流体结构紧耦合算法

从流固耦合系统的整体控制方程出发,推导出与流体控制方程一致的耦合等价方程,并得到基于耦合方程的压力泊松方程,通过求解耦合系统压力泊松方程和一致的等价方程就能获得耦合系统的解,而不需要直接求解整体耦合系统的控制方程,有利于降低求解自由度。预估-校正多步迭代格式用于耦合系统的时间推进,克服了传统迭代耦合方法由于时间不同步而产生较大数值误差的不足。应用该方法对附带局部突起的主动脉弓动脉瘤进行流固耦合分析,验证数值方法的可行性。     

A majority-logic device using an irreversible single-electron box

We describe a majority-logic gate device suitable for use in developing single-electron integrated circuits. The device consists of a capacitor array for input summation and an irreversible single-electron box for threshold operation. It accepts three binary inputs and produces a corresponding output, a complementary majority-logic output, by using the change in its tunneling threshold caused by the input signals; it produces a logical 1 output if two or three of the inputs are logical 0 and a logical 0 output if two or three of the inputs are logical 1. We combined several of these gate devices to form subsystems, a shift register and a full adder, and confirmed their operation by computer simulation. The gate device is simple in structure and powerful in terms of implementing digital functions with a small number of devices. These superior features will enable the device to contribute to the development of single-electron integrated circuits.     

Compact Rayleigh and Rician fading simulator based on random walk processes

This article describes a significantly improved sum-of-sinusoids-based model for the accurate simulation of time-correlated Rayleigh and Rician fading channels. The proposed model utilises random walk processes instead of random variables for some of the sinusoid parameters to more accurately reproduce the behaviour of wireless radio propagation. Every fading block generated using our model has accurate statistical properties on its own and hence, unlike previously proposed models, there is no need for time-consuming ensemble-averaging over multiple blocks. Using numerical simulation it is shown that the important statistical properties of the generated fading samples have excellent agreement with the theoretical reference functions. A fixed-point hardware implementation of the corresponding Rayleigh and Rician fading channel simulator on a field-programmable gate array (FPGA) is presented. By efficiently scheduling the operations, the reconfigurable fading channel simulator is compact enough that it can be efficiently used to simulate multipath scenarios and multiple-antenna systems (e.g. a 4 times 4 MIMO channel) using a single FPGA.     

Simulation study on discrete charge effects of SiNW biosensors according to bound target position using a 3D TCAD simulator

We introduce a simulation method for the biosensor environment which treats the semiconductor and the electrolyte region together, using the well-established semiconductor 3D TCAD simulator tool. Using this simulation method, we conduct electrostatic simulations of SiNW biosensors with a more realistic target charge model where the target is described as a charged cube, randomly located across the nanowire surface, and analyze the Coulomb effect on the SiNW FET according to the position and distribution of the target charges. The simulation results show the considerable variation in the SiNW current according to the bound target positions, and also the dependence of conductance modulation on the polarity of target charges. This simulation method and the results can be utilized for analysis of the properties and behavior of the biosensor device, such as the sensing limit or the sensing resolution.     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

A dielectric-modulated field-effect transistor for biosensing

Interest in biosensors based on field-effect transistors (FETs), where an electrically operated gate controls the flow of charge through a semiconducting channel, is driven by the prospect of integrating biodetection capabilities into existing semiconductor technology. In a number of proposed FET biosensors, surface interactions with biomolecules in solution affect the operation of the gate or the channel. However, these devices often have limited sensitivity. We show here that a FET biosensor with a vertical gap is sensitive to the specific binding of streptavidin to biotin. The binding of the streptavidin changes the dielectric constant (and capacitance) of the gate, resulting in a large shift in the threshold voltage for operating the FET. The vertical gap is fabricated using simple thin-film deposition and wet-etching techniques. This may be an advantage over planar nanogap FETs, which require lithographic processing. We believe that the dielectric-modulated FET (DMFET) provides a useful approach towards biomolecular detection that could be extended to a number of other systems.     

High-speed Josephson integrated circuit technology

The author describes recent progress in high-speed integrated circuits using niobium junctions. He briefly describes the circuit fabrication process and then introduces the modified variable threshold logic (MVTL) gate family. The lowest experimentally obtained MVTL OR-gate delay was only 2.5 ps with a power consumption of 17 μW/gate. This gate family is used in various high-speed logic circuits, such as 8-bit shift registers, 16-bit ALUs (arithmetic logic units), and 4-bit microprocessors. The author confirmed the high-speed operation of less than 10 ps per gate on average for these circuits. A novel high-sensitivity magnetic sensor using a SQUID (superconducting quantum interference device) was also developed. It is called a single-chip SQUID magnetometer because the feedback circuit, which is operated at room temperature is a conventional SQUID system, has been integrated on the same chip as the SQUID sensor itself     

Nanometer resolution stress measurement of the Si gate using illumination-collection-type scanning near-field Raman spectroscopy with a completely metal-inside-coated pyramidal probe

We have proposed an illumination-collection-type scanning near-field Raman spectroscopy (SNRS) with a completely gold metal-inside-coated (MIC) pyramidal probe without an optical aperture in order to detect the Raman spectra of fine Si devices for local stress measurements. The gold MIC pyramidal probe has been studied to act as a plasmon resonance near-field optical probe with high power using a finite differential time domain (FDTD) simulation and the prototyped SNRS. In the simulation, the propagated optical power can be made available for SNRS. In the experiments, it is clear that the prototyped SNRS enhanced the Si Raman peak signal by plasmon resonance and could measure the Si Raman peak shift by line scanning the Si gate region and the Si active layer. Furthermore, compressive and tensile stresses localized around the Si gate were demonstrated by the Si Raman peak shift with a resolution of about 10 nm. It is clarified that the proposed SNRS has the possibility of detecting the Raman spectra of a local area.     

High-performance simulator for digital audio class D amplifiers

A new transient analysis simulator for digital class D amplifiers, which significantly reduces the simulation time (more than ten-fold), and which provides an accurate and robust audio performance analysis, is presented in this study. This simulator, called a hybrid simulator, is of special interest because it provides a better compromise between time and accuracy when compared with previous work. This simulator consists in keeping the most representative states of the transient simulation to process an optimal simulation. The results obtained by this new technique are compared with standard transient simulations (Eldo) and with experimental measurements. The circuit under test has been designed on 0.13 μm CMOS technology and, an FPGA is used for digital modulator implementation.     

Simulation study of a field emission triode structure using carbon-nanotube emitters

The device level simulation analysis without considering nanometer geometry of the emissive material is carried out on a self-aligned gated field emission triode structure that can be used for low electric-field emissive materials such as carbon nanotubes. The electric properties of the device, such as electric-field distribution, pixel capacitance, and gate controllability, are simulated using a commercially available field solver based on the boundary-element method. The simulation results show that the depletion-mode operation can eliminate high electric field near the triple-junction regions and produce better uniform emission, comparing enhanced mode operation. The detail of the depletion mode operation is discussed. We also calculate the effect of the gate thickness on pixel emission current and suggest control of the variation of gate layer depostion within 3% in short distance and 20%-30% over the whole display area.     

Temperature dependence of current-voltage characteristics of polycrystalline diamond FETs: modelling and experiment

For the first time, a theoretical model for polycrystalline diamond (PCD) field effect transistors is proposed. The model is accompanied by an investigation of the single crystalline diamond (SCD) FET for the verification of material parameters employed in the simulation. The model runs on a device simulator, PISCES-IIB, and correctly accounts for the temperature-dependent shift of the I–V characteristics from pentode-like to triode-like behaviour as well as the temperature dependent pinch-off and saturation. Agreement between simulated and measured currents is obtained with a higher value of the activation energy for the dopant in PCD than in SCD, as has been reported for silicon.     

Assessment of human–machine interface design for a Chinese nuclear power plant

A nuclear power plant (NPP) is a complex system but requires high reliability. The human–machine interface (HMI) design plays very important role in reactor safety. This paper describes an assessment on HMI design of a Chinese NPP, using a software system named Dynamic Interaction Analysis Support (DIAS). DIAS can give not only quantitative indices for dynamically assessing the HMI design, but also allow modify the values of these indices by taking into account human error probability during specified emergent operation procedures. The operation procedures dealing with postulated accidents and transients recorded from a full-scale plant simulator in the training center of a Chinese NPP were selected as references. According to the results of simulation and analysis, the potential problems in the HMI design and the operation procedures were detected. Suggestions to improve the HMI design and the operation procedures were addressed.     

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Abstract

Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl) copper phthalocyanine (CuPc₆) were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs) in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO₂) as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS) resulted in values of 4×10^?2 cm² V^?1 s^?1 and 10⁶ for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.     

Single-electron transistors based on gate-induced Si island for single-electron logic application

The island size dependence of the capacitance components of single-electron transistors (SETs) based on gate-induced Si islands was extracted from the electrical characteristics. In the fabricated SETs, the sidewall gate tunes the electrically induced tunnel junctions, and controls the phase of the Coulomb oscillation. The capacitance between the sidewall gate and the Si island extracted from the Coulomb oscillation phase shift of the SETs with sidewall depletion gates on a silicon-on-insulator nanowire was independent of the Si island size, which is consistent with the device structure. The Coulomb oscillation phase shift of the fabricated SETs has the potential for a complementary operation. As a possible application to single-electron logic, the complementary single-electron inverter and binary decision diagram operation on the basis of the Coulomb oscillation phase shift and the tunable tunnel junctions were demonstrated.     

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail.     

An efficient solver of the saturation equation in liquid composite molding processes

A major issue in Liquid Composite Molding Process (LCM) concerns the reduction of voids formed during the resin filling process. Reducing the void content increases the quality of the composite and improves its mechanical properties. Most of modeling efforts on process simulation of mold filling has been focused on the single phase Darcy’s law, with resin as the only phase, ignoring the formation and transport of voids. The resin flow in a partially saturated region can be characterized as two phase flow through a porous medium. The mathematical formulation of saturation in LCM takes into account the interaction between resin and air as it occurs in a two phase flow. This model leads to the introduction of relative permeabilities as a function of saturation. The modified saturation equation is obtained as a result, which is a non-linear advection-diffusion equation with viscous and capillary phenomena. In this work, a flux limiter technique has been used to solve a modified saturation equation for the LCM process. The implemented algorithm allows a numerical optimization of the injected flow rate which minimizes the micro/macroscopic void formation during mold filling. Some preliminary numerical results are presented here in order to validate the proposed mathematical model and the numerical scheme. This formulation opens up new opportunities to improve LCM flow simulations and optimize injection molds.     

Interferometric laser imaging for droplet sizing revisited: elaboration of transfer matrix models for the description of complete systems

We report the development of an interferometric laser imaging for droplet sizing (ILIDS) numerical simulator. It is based on the use of generalized Huygens-Fresnel integrals associated to transfer matrices that describe the whole imaging setup. This simulator allows easy simulation of any kind of ILIDS setup. Simulations are shown to be in good agreement with experimental results. This simulator offers important perspectives in the design, realization, and calibration of ILIDS instruments, as airborne instruments, or in situ measurements in flows.