Stress-induced leakage current of tunnel oxide derived from flashmemory read-disturb characteristics

This paper describes the characteristics of the stress-induced leakage current of tunnel oxide derived from flash memory read-disturb characteristics. The following three items were newly observed. First, the threshold voltage shift (ΔV_th) of the memory cell under the gate bias condition (read disturb condition) consists of two regions, a decay region and a steady-state region. The decay region is due to both the initial trapping or detrapping of the carriers in the tunnel oxide and the decay of the stress-induced leakage current of the tunnel oxide. The steady-state region is determined by the saturation of the stress-induced leakage current of the tunnel oxide. Second, the read disturb life time is mainly determined by the steady-state region for the oxide thickness of 5.7-10.6 nm investigated here. Third, a high-temperature (125°C) write/erase operation degrades the steady-state region characteristics in comparison with room temperature (30°C) operation. Therefore, accelerated write/erase tests can be carried out at higher operation temperatures     

新型嵌入式BeNOR结构Flash存贮器

提出了一种能根据嵌入式应用系统容量的不同而灵活选择字节擦除和块擦除两种不同擦除模式的BeNOR阵列结构,该结构采用沟道热电子注入进行"写"操作,采用分离电压法负栅压源极F-N隧道效应进行擦除.对分离电压法负栅压源极F-N隧道效应擦除的研究表明,采用源极电压为5V,栅极电压为-10V的擦除条件,不仅能很好地控制擦除后的阈值电压,而且当字线宽度小于等于64时,源极电压导致的串扰效应能得到很好的抑制.研究表明该结构具有编程速度高、读取速度高、可靠性高及系统应用灵活的特点,非常适宜于在1M位以下的嵌入式系统中应用.     

A novel MONOS nonvolatile memory device ensuring 10-year dataretention after 107 erase/write cycles

A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor (MONOS) structure whose top oxide is fabricated by chemical vapor deposition (CVD) on the nitride is proposed. This CVD oxide is densified by pyrogenic annealing and has stoichiometric SiO₂ characteristics. Its potential barrier, which prevents stored charges from decaying through the top oxide to the gate, thus becomes sharper than that of the thermally grown top oxide used in the conventional MONOS structure. For comparison between the proposed MONOS, conventional MONOS, and MNOS structures, three devices were fabricated on the same process line. The 16.7-nm nitride thickness in combination with a top oxide thickness of 4.0 nm results in a gate capacitance equivalent to that of the conventional NMOS structure with a 23.5-nm nitride thickness. Moreover, an asymmetric erase/write programming voltage has been adapted to the MONOS device operation by considering both erased-state degradation and written-state retention. At 85 °C, the proposed MONOS device has 10⁷-cycle endurance with 10-year data retention     

Improving radiation hardness of EEPROM/flash cell by N2Oannealing

The effects of an N₂O anneal on the radiation effects of a split-gate electrical erasable programmable read only memory (EEPROM)/flash cell with a recently-proposed horn-shaped floating gate were studied. We have found that although the cells appear to survive 1 Mrad(Si) Co⁶⁰ irradiation without data retention failure, the write/erase cycling endurance was severely impeded after irradiation. Specifically, the write/erase cycling endurance was degraded to 20 K from the pre-irradiation value of 50 K. However, by adding an N₂ O annealing step after the interpoly oxidation, the after-irradiation write/erase cycling endurance of the resultant cell can be significantly improved to over 45 K. N₂O annealing also improves the after-irradiation program and erase efficiencies. The N₂O annealing step therefore presents a potential method for enhancing the robustness of the horn-shaped floating-gate EEPROM/flash cells for radiation-hard applications     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

A new technique for determining the capacitive couplingcoefficients in flash EPROMs

A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures     

A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Read disturb in flash memories: reliability case

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.     

A 256-Mb multilevel flash memory with 2-MB/s program rate for massstorage applications

A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm² die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V_th. The effect of adjacent memory cell's V_th is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V_th. In the -5-75°C range, memory threshold V_th deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector     

Investigation of read disturb in split-gate memory and its feasible solution

The intrinsic read disturb mechanism in split-gate memory cells has been studied based on large amounts of experimental data and simulation results of 0.11 μm NOR SuperFlash® technology memory cells. It is shown that non-planar Floating Gate (FG) structure induced field enhance effect helps to cause Fowler-Nordheim Tunneling (F-N tunneling) in tunnel oxide during read operation, which will further lead to the leakage of electrons from FG to Word Line (WL). Then, the sensitivity of read disturb to process variation is investigated to expound the difference between typical cells and weak cells. The experiment has also demonstrated the weakening of read disturb due to induced tunnel oxide traps after program/erase (P/E) cycles. Based on these findings, we have rationally proposed possible solutions to reduce the read disturb on the perspectives of chip testing. The study of intrinsic read disturb mechanism is significant to the scaling of split-gate memory technology as well as to the assessment of read disturb risk in split-gate memory products.     

A simple and efficient self-limiting erase scheme for highperformance split-gate flash memory cells

This paper presents a fast self-limiting erase scheme for split-gate flash EEPROMs. In this technique the conventional erasing is rapidly followed by an efficient soft programming to correct for over-erase within the given voltage pulsewidth. The typical erasing time is about 400 ms and the final erased threshold voltage is accurately controlled via the base level read mode voltage within 0.3 V. The proposed scheme can he used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using aNAND flash memory technology

A 3.3-V 16-Mb nonvolatile memory having operation virtually identical to DRAM with package pin compatibility has been developed. Read and write operations are fully DRAM compatible except for a longer RAS precharge time after write. Fast random access time of 63 ns with the NAND flash memory cell is achieved by using a hierarchical row decoder scheme and a unique folded bit-line architecture which also allows bit-by-bit program verify and inhibit operation. Fast page mode with a column address access time of 21 ns is achieved by sensing and latching 4 k cells simultaneously. To allow byte alterability, nonvolatile restore operation with self-contained erase is developed. Self-contained erase is word-line based, and increased cell disturb due to the word-line based erase is relaxed by adding a boosted bit-line scheme to a conventional self-boosting technique. The device is fabricated in a 0.5-μm triple-well, p-substrate CMOS process using two-metal and three-poly interconnect layers. A resulting die size is 86.6 mm², and the effective cell size including the overhead of string select transistors is 2.0 μm²     

A novel nonvolatile memory cell suitable for both flash andbyte-writable applications

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors     

A New Architecture for High-Density High-Performance SGT nor Flash Memory

In order to overcome the limitation of a conventional NOR flash memory, we propose a new architecture using a surrounding gate transistor (SGT) NOR flash memory to realize both Fowler-Nordheim (FN)-tunneling program and high-speed random access read operation. The SGT NOR flash memory cell has a 3D structure, in which the source, gate and drain are vertically stacked. The gate surrounds a silicon pillar. The source line of a diffusion layer and the metal bit line (BL) are wired to the bottom and the top of the silicon pillar, respectively. The BL and SL are arranged in the same column direction and the gate line is wired in the row direction. This structure enables the same voltage to be simultaneously applied to both the SL and BL of the same column. Therefore, the SGT NOR flash memory cell can be written and erased by the FN-tunneling mechanism. In read operation, the metal common SL is connected with the SL every 16 memory cells to reduce the resistance of the SL. As a result, a read current is improved and a high-speed read operation can be achieved. Furthermore, the SGT NOR flash memory adapts to 50-nm node to obtain a compact cell area of 6.6 and a large read current of 72 muA; the cell area can be reduced by 54% and a read current increase by 227% compared to the conventional NOR flash memory. Owing to high-density and high-speed features, the SGT NOR flash memory is a promising structure for the future high-density and high-performance flash memory.     

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.     

Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operation

The impact of program/erase (P/E) cycling on drain disturb in NOR Flash EEPROM cells under channel hot electron (CHE) and channel-initiated secondary electron (CHISEL) programming operation is studied. Charge gain disturb increases and charge loss disturb decreases after cycling under CHE and CHISEL operation. Carefully designed experiments and fullband Monte Carlo simulations were used to explain this behavior. P/E cycling induced degradation in gate coupling coefficient and the resulting increase in source/drain leakage, reduction in band-to-band tunneling and change in carrier injection area seems to explain well the behavior of CHE and CHISEL drain disturb after cycling.     

Performance of the 3-D PENCIL flash EPROM cell and memory array

A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3× larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising     

Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology

The negative threshold voltage (V/sub t/) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V/sub t/ shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V/sub t/ shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V/sub t/ drift is proposed.