Capless rapid thermal annealing of GaAs using a graphite susceptor

The results of experiments performed to evaluate the use of a commercially available rapid thermal annealer (RTA) with a graphite susceptor for capless rapid thermal annealing to activate implants in GaAs are reported. The interior of the susceptor was easily charged with As by annealing a sacrificial GaAs wafer. Wafers annealed face up in the charged susceptor showed no evidence of surface degradation (due to preferential loss of As) and no decrease in implant activation (peak doping) when compared to dielectric (SiO₂) capped anneals. Over 50 wafers have been annealed without recharging the susceptor. In addition, slip on 3-in wafers was almost completely eliminated due to the reduction of radial temperature gradients. It is concluded that capless RTA in a commercially available graphite susceptor appears to be a viable annealing technique for activating implants in GaAs and related III-V materials and is suitable for a production environment     

Formation of nickel disilicide using nickel implantation and rapid thermal annealing

Transmission electron microscopy (TEM), secondary ion mass spectroscopy (SIMS), and x-ray photoemission spectroscopy (XPS) have been used to investigate the nucleation, growth, and ripening behavior of nickel-disilicide precipitates formed by Ni implantation in an amorphous-Si layer on (100) Si and followed by a two-step annealing treatment. The TEM and XPS results show that amorphous-disilicide precipitates are formed in a depth of ∼21 nm in the amorphous-Si layer when pre-annealed at 380°C for 30 sec. It is also shown that the second-step annealing at temperatures in the range of 450–600°C causes the amorphous precipitates to transform to randomly oriented crystalline ones embedded in the amorphous-Si layer. Annealing above 550°C is shown to induce the crystallization of amorphous Si by solid-phase epitaxial growth (SPEG). It is further shown that, in a prolonged annealing at high temperatures, the disilicide has dissolved and reprecipitated on the Si surface. Based on the roles of the silicide-mediated crystallization (SMC), the dissolution and reprecipitation of silicides, and SPEG, possible mechanisms are given to explain how the surface-disilicide islands are formed during annealing at temperatures of 550–950°C.     

Phosphorus-overpressure rapid thermal annealing of indium phosphide

A rapid thermal annealing technique for InP is described in which a controllable phosphorus overpressure, generated by heating red phosphorus, suppresses the dissociation of InP at required annealing temperatures. Two annealing configurations were used to independently study the effects of phosphorus overpressures, anneal temperatures and gas flow rates on the post-anneal electrical and morphological properties of low dose Si-implanted InP:Fe. The advantage of phosphorus overpressure annealing over close-contact annealing is shown, and comparison is made with Si₃N₄ encapsulated annealing. Gas flow velocities close to the sample are found to significantly affect the surface morphology, and a static layer immediately above the sample is found to be beneficial.     

Au/TiN/WSi-gate self-aligned GaAs MESFETs using rapid thermal annealing method

Au/TiN/WSi-gate self-aligned GaAs MESFETs were fabricated using the rapid thermal annealing method to reduce the gate resistance of the FETs. The gate resistance Rg was 4.2 ? (Lg=1.5 ?m, Wg=400 ?m), just 1/20 of that of the WSi-gate FET. The maximum frequency of oscillation fmax of the Au/TiN/WSi-gate FETs was improved to be about twice that of WSi-gate FETs.     

Indium out-diffusion from silicon during rapid thermal annealing

The out-diffusion of indium (In) from In-implanted silicon (Si) samples that includes bare Si, samples with an oxide-cap layer, nitride-cap layer, and nitride/oxide/Si sandwiched samples, is investigated. The dose loss of In with respect to different implant energies, doses, and soak times during rapid thermal annealing (RTA) is quantified. Experimental results of bare Si samples show that over 90% of In out-diffusion happens within 1 sec of soak time in the RTA process. In the capped samples, In rapidly diffuses through the oxide layer and stops at the nitride/oxide interface. In gets piled up at the interface of Si/oxide and oxide/nitride, and nitride very efficiently prevents In out-diffusion from the oxide layer out to the nitride layer. In addition, In gets more segregated in the Si surface in the presence of boron.     

Ultra high temperature rapid thermal annealing of GaN

All of the major acceptor (Mg, C, Be) and donor (Si, S, Se and Te) dopants have been implanted into GaN films grown on Al₂O₃ substrates. Annealing was performed at 1100–1500°C, using AlN encapsulation. Activation percentages of ≥90% were obtained for Si⁺ implantation annealed at 1400°C, while higher temperatures led to a decrease in both carrier concentration and electron mobility. No measurable redistribution of any of the implanted dopants was observed at 1450°C.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

High-sensitivity porous silicon photodetectors fabricated throughrapid thermal oxidation and rapid thermal annealing

The sensitivity of a porous silicon Schottky barrier photodetector is much improved through rapid thermal oxidation and rapid thermal annealing processes. Under our optimum preparation conditions, photocurrent can reach about 21 mA (under 22.4 mW/cm² tungsten lamp illumination) and dark current is about 5.4 μA (at reverse bias of 10 V). The quantum efficiencies are about 90% at wavelengths shorter than 750 nm and 80%-70% in the wavelength range 750-1050 nm     

Direct silicidation of Co on Si by rapid thermal annealing

Rapid thermal annealing is used to form cobalt silicide directly on unimplanted as well as B-, As-, and P-implanted wafers. The films are characterized by sheet resistance, X-ray diffraction, SEM, TEM, SIMS, and contact resistance measurements. The direct silicidation of Co on Si by rapid thermal annealing yields smooth low-resistivity films with minimal dopant redistribution.     

Electrical characteristics of Be-implanted GaAs activated by rapid thermal annealing

Be-implanted GaAs are annealed by rapid thermal annealing (RTA) using halogen lamps. Electrical properties of the annealed GaAs are investigated, emphasizing those at 77K for application to the p+-layer of Be-implanted WSix-gate self-aligned two-dimensional hole gas (2- DHG) FET. An electrical activation of 90 percent (for 2.0 × 10¹³cm^-2) or 80 percent (for 2.2 × 10¹⁴cm^-2) is obtained. An annealing temperature dependence of carrier freezing at 77K is observed for higher dose samples. The phenomenon is attributed to the redistribution of impurity atoms near the high-concentration peak.     

Flat band voltage shift and oxide properties after rapid thermal annealing

The flat band voltage (V_fb) shift observed for MOS samples exposed to rapid thermal annealing (RTA) (N₂, 20 s, 1040°C) is examined for (1 0 0), (1 1 0) and (1 1 1) orientation-silicon substrates. Using a mercury gate C–V system, the V_fb shift can be attributed to changes in the electronic properties of the oxide layer and not polysilicon gate effects, as had previously been suggested. In addition, this work indicates that the flat band voltage shift results from a reduction of interface and fixed oxide charge due to the RTA process. The interface and oxide charge densities are related to the density of available bonds for each surface orientation, both before and after an RTA step. Based on these results, we argue that the V_fb shift following RTA is primarily due to a reduction of fixed positive charge in the oxide, and to a lesser degree, to a reduction of negative interface charge. The net effect is that the RTA step reduces the total oxide charge density.     

Sensitivity analysis of ion implanted silicon wafers after rapid thermal annealing

In this study, we have investigated sensitivities of the ion implanted silicon wafers processed by rapid thermal annealing (RTA), which can reveal the variation of sheet resistance as a function of annealing temperature as well as implantation parameters. All the wafers were sequentially implanted by the arsenic or phosphorous implantations at 40, 80, and 100 keV with the dose level of 10¹⁴ to 2 × 10¹⁶ ions/cm². Rapid thermal annealing was carried out for 10 s by the infrared irradiation at a temperature between 850 and 1150°C in the nitrogen ambient. The activated wafer was characterized by the measurements of the sheet resistance and its uniformity mapping. The values of sensitivities are determined from the curve fitting of the experimental data to the fitting equation of correlation between the sheet resistance and process variables. From the sensitivity values and the deviation of sheet resistance, the optimum process conditions minimizing the effects of straggle in process parameters are obtained. As a result, a strong dependence of the sensitivity on the process variables, especially annealing temperatures and dose levels is also found. From the sensitivity analysis of the 10 s RTA process, the optimum values for the implant dose and annealing temperature are found to be in the range of 10¹⁶ ions/cm² and 1050-1100°C, respectively. The sensitivity analysis of sheet resistance will provide valuable data for accurate activation process, offering a guideline for dose monitoring and calibration of ion implantation process.     

A phenomenon of charge trapping saturation induced by rapid thermal annealing

In this paper, we investigate the impact of the rapid thermal annealing (RTA) temperature on the performance degradation of NMOS devices, due to hot electrons. Our results indicate that RTA with a higher temperature achieves a higher interface barrier and induces a greater initial positive trapped charge. We observe a new three-section degradation phenomenon during DC stress at a low RTA temperature of 875°C, along with the discovery of a non-monotonic substrate current degradation which finally saturates. We note that the non-monotonicity is induced by a trapped charge polarity change, and the saturation is induced by a progression of an injected charge pocket toward the channel. This study provides an insight into the analysis of device degradation vs the RTA temperature, and should be useful for reliability optimization in process integration.     

Study of GaN thin layers subjected to high-temperature rapid thermal annealing

A detailed study of the effect of rapid thermal annealing in a N₂ or Ar atmosphere on the properties of thin GaN layers grown by molecular-beam epitaxy on sapphire substrates was performed. After rapid thermal annealing, an enhancement of the crystal quality of such films was observed. Low-temperature photoluminescence measurements revealed a substantial increase in impurity recombination near the fundamental absorption edge after a rapid high-temperature anneal in a nitrogen atmosphere. A significant decrease in the impurity photoluminescence of the GaN films with protective SiO₂ coatings was observed following the anneals. Fiz. Tekh. Poluprovodn. 32, 1175–1180 (October 1998)     

Manufacturability issues related to transient thermal annealing oftitanium silicide films in a rapid thermal processor

Transient thermal annealing of sputtered titanium films in a rapid thermal processor (RTP) is critically evaluated from the viewpoint of manufacturability-related considerations. In particular, the thin-film properties of the resulting titanium silicide on polysilicon and silicon, process uniformity, and unit step wafer yield of high-density scaled device structures are investigated. The experimental results suggest that RTP silicides show good thin-film properties for manufacturability on planar wafer surfaces. Transient thermal gradients in an RTP system are shown to cause substantial variations in the electrical and structural properties of TiSi_x films formed on silicon substrates with varying substrate thicknesses. Closed-loop temperature control in an RTP reactor provided stoichiometrically identical TiSi_x films with negligible substrate thickness dependence. The experimental results also suggest that careful wafer surface temperature control is needed when forming titanium silicide films on nonplanar silicon surfaces, silicon trenches, and process monitor wafers without predetermined wafer thicknesses     

Device and material properties of pseudomorphic HEMT structuressubjected to rapid thermal annealing

The device-related effects of rapid thermal annealing (RTA) on the electrical and optical properties of planar-doped AlGaAs/InGaAs/GaAs high-electron-mobility transistor structures grown by molecular beam epitaxy were investigated. Specifically, electrical and optical characterization techniques such as capacitance versus voltage, current versus voltage, Hall effect, and photoluminescence have been applied to study the effects that typical III-V compound semiconductor rapid thermal processes (RTPs) have on the properties of pseudomorphic AlGaAs/InGaAs/GaAs structures for two different values of In mole fraction content. The effect and stability of the indium mole fraction on both heterostructure and device integrity with respect to RTA schedule has been investigated in detail     

High-performance submicrometer undergated thin-film transistorswithout high-temperature rapid thermal annealing or plasma hydrogenation

High-performance submicrometer undergated thin-film transistors (TFTs) are fabricated without using high-temperature rapid thermal annealing or plasma hydrogenation. These processes are used in the state-of-the-art devices, but avoided in current manufacturing. For a 0.35-μm×0.35-μm device and a 0.7-μm×0.5-μm device, I_ON of 3 and 1.2 μA are obtained with ON/OFF current ratios of 4×10⁵ and 1.2×10⁸ , respectively, very close to that of state-of-the-art devices. A new lightly-doped-drain (LDD) structure is employed to improve I_ON reproducibility, which is difficult to achieve for deep-submicrometer devices with the conventional lightly-doped-offset (LDO) structure     

Improvement of GaAs/AlGaAs quantum well laser diodes by rapid thermal annealing

Post-growth annealing is shown to improve the laser diode quality of GaAs/AlGaAs graded-index separate confinement heterostructure quantum well laser diode structures grown at a nonoptimal substrate temperature lower than 680°C by molecular beam epitaxy. Reduction by a factor of up to three in the threshold current was accompanied by a reduction in the interface trap density. The reduced threshold current is still higher than that of laser diodes grown at the optimal temperatures which are between 680 and 695°C. The improvement in laser diode performance is ascribed to the reduction of interface nonradiative recombination centers.     

Multi-step rapid thermal annealing of boron and indium implanted Hg1−xCdxTe

In this work, we are reporting the use of a two-step rapid thermal annealing (RTA) process (250°C, 100s+340°C, 30s) for the annealing of Hg_1−xCd_xTe (MCT) implanted layers over p-type (x=0.22) substrates. We report a high value of electrical activation (70%) of the indium implants after this short RTA treatment in inert Ar atmosphere. The need of two RTA steps in the annealing recipe is shown, and so the role played by each of them: the first step annihilates the implantation damage, while the second one produces the impurity electrical activation. However, for the boron case, no electrical activity was found after several annealing processes, behaving as an inert species for the case of this bulk MCT material. We also point out the change on the substrate electrical characteristics induced by the thermal treatments, and report the convenience of a subsequent low temperature furnace annealing (200°C, 72 h) to reduce back the bulk carrier concentration to values low enough to achieve an n⁺-p IR detector structure.     

Effect of rapid thermal annealing on deep level defects in the Si-doped GaN

Rapid thermal annealing effects on deep level defects in the n-type GaN layer grown by metalorganic chemical vapor deposition (MOCVD) have been characterized using deep level transient spectroscopy (DLTS) technique. The samples were first characterized by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The measurements showed that the barrier height of the as-grown sample to be 0.74 eV (I-V) and 0.95 eV (C-V) respectively. However, the Schottky barrier height of the sample annealed at 800 °C increased to 0.84 eV (I-V) and 0.99 eV (C-V) respectively in nitrogen atmosphere for 1 min. Further, it was observed that the Schottky barrier height slightly decreased after annealing at 900 °C. DLTS results showed that the two deep levels are identified in as-grown sample (E1 and E3), which have activation energies of 0.19 ± 0.01 eV and 0.80 ± 0.01 eV with capture cross-sections 2.06 × 10⁻¹⁷ cm² and 7.68 × 10⁻¹⁸ cm², which can be related to point defects. After annealing at 700 °C, the appearance of one new peak (E2) at activation energy of 0.49 ± 0.02 eV with capture-cross section σ_n = 5.43 × 10⁻¹⁷ cm², suggest that E2 level is most probably associated with the nitrogen antisites. Thermal annealing at 800 °C caused the E1 and E3 levels to be annealed out, which suggest that they are most probably associated with the point defects. After annealing at 900 °C the same (E1 and E3) deep levels are identified, which were identified in as-grown n-GaN layer.