New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity     

Applications of composite BiCMOS transistors

The concept of the composite CMOS transistor is generalised and extended to include both, composite bipolar and composite BiCMOS transistors. Two versions of the BiCMOS device and its applications in some linear circuits to reduce supply voltage requirements and increase effective transconductance are discussed. Experimental results using transistor arrays are presented.<>     

An accurate analytical BiCMOS delay expression and its applicationto optimizing high-speed BiCMOS circuits

A scheme for optimizing the overall delay of BiCMOS driver circuits is proposed in this paper. Using this optimization scheme, it is found that the delay is minimized when the maximum collector current of the bipolar transistors is equal to the onset of high current effects. Using this assumption, an accurate BiCMOS delay expression is derived in terms of the bipolar and MOS device parameters. The critical device parameters are then identified and their influence on the circuit speed discussed. An overall circuit delay expression for optimizing BiCMOS buffers is derived and a comparison made with CMOS buffers. It is shown that BiCMOS circuits have a speed advantage of 1.7 or an area advantage of about 5 for 2-μm feature sizes. In order to predict the future performance of BiCMOS circuits, a figure of merit is derived from the delay expression. Using the figure-of-merit expression, it is seen that future BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicrometer dimensions under constant load capacitance assumption     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Effect of reverse base current on bipolar and BiCMOS circuits

A detailed study on the effect of reverse base current (RBC) on the switching behavior of bipolar BiCMOS circuits utilizing advanced high-performance bipolar transistors is presented. It is shown that as the collector doping N_c is increased to overcome the Kirk effect (base stretching) during the switching transient, the avalanche-generated reverse base current in the collector-base junction may cause problems for bipolar output devices switching out of saturation. A basic bipolar inverter and various BiCMOS driver circuits were simulated based on measured avalanche multiplication factors from advanced bipolar transistors with various collector doping N _c. In the case of the basic bipolar inverter, the reverse base current may prevent the switching device from being shut off completely during the on-to-off transition and a self-sustained state may result which reduces the output voltage swing. For the common-emitter (CE) BiCMOS driver, a similar self-sustained state may also occur with the added adverse effect of excessive leakage in standby. Design and scaling considerations are discussed     

BiCMOS logic circuit for single-battery operation

A novel BiCMOS logic circuit is described that provides highspeed rail-to-rail operation with only one battery cell (1-1.5 V). The proposed circuit utilises a novel pull-down scheme that involves bootstrapping the base of the pull-down p-n-p bipolar junction transistor to a negative potential during the pull-down transient period. Circuit simulations have shown that the proposed circuit outperforms the transient-saturation full-swing BiCMOS and the bootstrapped bipolar circuits in terms of delay, power and cross-over capacitance for all simulated supply voltages     

CMOS-compatible lateral bipolar transistor for BiCMOS technology.II. Experimental results

For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of h_FE, BV_CEO, R _CS, f_Tmax, and r_bb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors     

BiCMOS circuitry: the best of both worlds

The growing use of BiCMOS circuits, which benefit from the combination of low CMOS power consumption and high bipolar speed, is examined. The tradeoffs that BiCMOS circuits entail and the drawbacks that have hindered their wide adoption, especially for digital applications, are discussed. The growing opportunity for BiCMOS, as CMOS ICs have become more complicated and the benefits of scaling them less pronounced and harder to realize, is noted. The three basic reasons for using BiCMOS, namely, analog compatibility, increased performance, and reduced system costs, are discussed     

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (Hβ-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of Hβ-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, Hβ-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of Hβ-BiCMOS gate circuits     

Advances in bipolar VLSI

Bipolar IC processes are reviewed, and the impact of BiCMOS technology on bipolar VLSI is discussed. The discussion covers standard emitter-coupled-logic (ECL) circuit configuration, on-chip line driving, output circuitry, series gating, ECL versus CML (current-mode logic), differential logic, noise margins, interconnect capacitance, bipolar VLSI transistor design and scaling, and processes for ECL VLSI     

Integration of a double-polysilicon emitter-base self-alignedbipolar transistor into a 0.5-μm BiCMOS technology for fast 4-MbSRAM's

The single-polysilicon non-self-aligned bipolar transistor in a 0.5-μm BiCMOS technology has been converted into a double-polysilicon emitter-base self-aligned bipolar transistor with little increase in process complexity. Improved bipolar performance in the form of smaller base resistance and base-collector capacitance, larger knee current, higher peak cutoff frequency, and shorter ECL gate delay has been demonstrated. This technology will prove useful in meeting the requirements for higher performance in fast, high-density, SRAM circuits     

Optimization-based placement algorithm for BiCMOS leaf cellgeneration

We present a transistor placement algorithm for the automatic layout synthesis of logic and interface cells comprised of a mixture of MOS and bipolar devices. Our algorithm is applicable to BiCMOS logic cells, ECL logic cells as well as TTL, CMOS and ECL compatible input/output (I/O) cells. The transistor placement problem is transformed into a layout floorplan design problem with a mixture of rigid and flexible modules. A constructive “branch-and-bound” algorithm is used to minimize the area of synthesized circuits subject to pre-placement constraints. Experimental results indicate that the algorithm can produce efficient placements under fixed-height constraints. The design space exploration mechanism can be controlled by the user so as to apportion computing resources judiciously     

Bi-CMOS技术进展(下)

三、Bi-CMOS模拟/数字电路 随着电子系统复杂性的增加以及对可靠性要求的提高,过去那种将模拟电路和数字电路通过PC板互连起来的方法已经不适应。因此,实现A/D LSI已经成为人们追求的目标。这种芯片不仅在数字通讯、测量仪器、图像处理等方面有广泛用途,而且在民用领域,如照像机的自动曝光、录相机的自动聚焦、马达控制、声音的合成和识别等方面也有广阔的市场。     

Computing multivalued input-output Characteristics in the circuits containing bipolar transistors

The paper deals with dc circuits including bipolar transistors represented by the Ebers-Moll model. An important question how to efficiently compute multivalued input-output characteristics of these circuits is considered. A switching variables approach for tracing a multivalued single-branched characteristic, which can be considered as some kind of continuation method, is developed. A new strategy of switching variables is proposed and the generalized implicit function theorem is used as the mathematical background. Unfortunately, this approach suffers from major shortcomings when it is directly applied to bipolar transistor circuits, due to specific nonlinearities of the transistor model, causing the sharp-turning-point problem. To overcome this problem, a variable transformation is proposed, which leads to smooth solution curves. An efficient algorithm combining the developed variant of switching variable method with the proposed transformation is described. A generalized version of the algorithm enables us to compute multivalued characteristics composed of disconnected branches, under the assumption that at least one point on each branch can be found. It is illustrated via four examples of realistic transistor circuits including a voltage regulator, the Schmitt trigger, a line receiver, and their combination.     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation     

Low-voltage, low-power BiCMOS digital circuits

A new BiCMOS buffer circuit, for low-voltage, low-power environment, is presented. The circuit is based on the deep submicron technology and utilizes the parasitic bipolar transistors associated with the CMOS structure. The analysis, simulations and SPICE results confirm the functionality of the circuit and its speed and voltage swing superiority, compared with conventional BiCMOS circuits at low supply voltages     

A new technique for forming a shallow link base in a doublepolysilicon bipolar transistor

A new technique is presented for forming a shallow link base in a double polysilicon bipolar transistor. This method is easily integrated into an advanced BiCMOS process, making use of a disposable polysilicon spacer technology for MOSFET LDD formation. This new scheme allows independent optimization of active and link base regions while providing improvements in base-emitter breakdown and resistance to bipolar hot carrier degradation     

New ECL gate in BiFET process

An ECL gate is implemented as a combination of bipolar and MOS circuits in a BiFET process is presented. The resulting ECL gate exhibits an improved speed-power product over circuits presented in the past. Owing to its reduced power consumption this gate allows a higher level of integration for ECL. The process used is standard BiCMOS.<>     

Substrate coupling evaluation in BiCMOS technology

The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-μm BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring