一种面向光收发器的ps级光脉冲产生器

由于高速光开关在光互连通信中越来越广泛的应用,光开关的开关速度直接影响了整个光链路的传输速率,因此对驱动光开关产生长周期窄脉冲光信号的驱动电路的性能及集成度有了更高要求。基于光电集成工艺和高速光脉冲队列技术的发展,提出了一种应用于光SerDes收发器的集成ps级窄脉冲光信号产生器。该产生器为CMOS电路产生脉宽精确可调的长周期窄脉冲,在SMIC 0.13μm CMOS工艺下可获得窄至25ps的脉冲输出,其电源电压范围宽达1.4V~2.5V,时钟频率也可由数kHz到4GHz,同时可移植到不同的CMOS工艺平台。     

基于CPLD+LVPECL可调窄脉冲发生器的设计与实现

采用CPLD和具有速度极快的LVPECL门电路来实现脉宽可调的窄脉冲信号。利用CPLD提供的10 MHz激励信号和对延时芯片进行写延时控制字来产生所需脉宽。测试结果表明,该可调窄脉冲发生器能产生500 ps～20 ns范围内的脉宽可调、幅度约为400 mV的脉冲信号。     

基于XAUI协议的10 Gb/s光纤通信系统

为提高光纤通信系统的数据吞吐量,增加系统集成度,提出基于附加单元接口(XAUI)协议的10 Gb/s光纤通信系统的设计方法。采用Virtex-5 FPGA内置RocketI/O收发器的通道绑定技术实现用户逻辑至光模块之间的数据通路。利用FPGA及XPAK光模块使以往复杂、高成本的高速光纤通信系统得到简化。     

一种超宽带多波形参数的脉冲成形方法

介绍了一种多波形参数的超宽带脉冲信号成形方法,实现了信号周期、相位、脉宽以及幅度等的在线可调.该方法的特点在于可产生长周期下的超窄脉冲,实现高分辨率的相位同步、脉宽调整,并具有皮秒级的边沿和抖动,可用于不同目的的通信应用场合.     

基于半导体开关皮秒脉冲发生器的研制

本文对光导开光的原理、特性进行了分析。利用高压电源对储能电容充电,激光器在接到触发脉冲指令时,发出脉宽为2ns的光脉冲信号驱动光导开关,储能电容内存储的能量通过光导开关释放到取样电阻上,输出高压脉冲信号。通过对电路基本参数的仿真,得到了光导开关在2ns激光脉冲控制下,输出高压脉冲与控制光脉冲响应良好,上升时间为169ps,脉宽为2ns。     

一种用于机群系统的双环光互连网络性能分析

高性能计算机网络对带宽的需求,使得如何提供高带宽的互连网络以及充分利用互连网络的固有带宽度为一个研究焦点。基于Linux操作系统,以千兆光互连接口卡为网络接口,设计实现了一种可用于机群系统的双环光互连网络。介绍了光互连网接口卡的基本结构,接口卡驱动软件的设计方法,双环光互连网络的拓朴结构及其特性。分析测试了光互连网络的通信性能,指出了影响系统整体性能的关键因素。     

一种高性能脉冲信号处理电路模块

针对电力电子器件驱动脉冲信号性能指标多、要求高、处理难度大的问题,设计并制作一种高性能脉冲信号处理电路模块,采用EDA高速电路技术完成设计,LTspice对电路系统仿真并进行实验测试,测试指标相比国内研究现状有显著提高,实现1 MHz的高速脉冲正向整流,输出电平可控,脉宽调节范围达到20%至60%,上下沿时间控制在25 ns以内,其中下降沿时间低至13 ns,传输延时调节范围20 ns至110 ns,2 MHz脉冲信号各项指标也得到大幅提升,从而有效提高驱动电路与主电路效率。进一步优化器件的选择与布局并采用更精密的制作工艺,有望处理频率高达5 MHz的脉冲信号,使电力电子电路更加集成与高效。     

基于FPGA的10Gbps光互连方案设计与验证

针对光、电传输特点和高速互连网络的特殊要求,通过分析光互连技术的发展历史和研究现状,提出了10Gb/s光互连技术可行性的设计方案;并为了验证该方案的可行性,采用试验的方式,完成了基于10Gb/s光互连的PCB实验板设计.从实验板的设计可发现:Framer FPGA在传统电互连和光互连间提供相应的协议转换和速率转换起着关键作用.     

面向HPC和DC的可重构光互连网络体系结构综述

互连网络是高性能计算系统和数据中心的核心组件之一,也是决定其系统整体性能的全局性基础设施。随着高性能计算、云计算和大数据技术的迅速发展,传统的电互连网络在性能、能耗和成本等方面无法满足高性能计算应用和数据中心业务的大规模可扩展通信需求,面临着严峻的挑战。为此,近年来相关研究者提出了多种面向高性能计算和数据中心的可重构的光互连网络结构。首先阐明了光互连网络相对于电互连网络的优势;然后介绍了几种典型的可重构光互连网络体系结构,并对其特点进行了分析比较;最后探讨了可重构光互连网络的发展趋势。     

光互连计算机体系结构研究

本文首先介绍了光互连技术和并行计算技术的发展现状。光互连技术具有高互连带宽、低功耗、高互连密度等特性 ,这些特性使得光互连技术在提高系统性能、减少系统体积、降低系统成本等方面将发挥重要作用。提出了一种采用自由空间光互连技术的计算机体系结构模型。这种模型能够充分利用自由空间光互连技术高互连密度和高互连带宽的特点 ,同时能够由数据驱动进行计算 ,具有较高的并行效率 ,采作 RAW结构中使用的 Benchmark程序进行的模拟证明了这种结构的较高并行效率。自由空间光互连技术所基于的器件技术与工艺已经日益成熟 ,如采用倒焊工…     

基于硅光子的片上光互连技术研究

随着芯片半导体工艺的发展,芯片集成度不断提高,单个芯片上所能容纳的计算核心数越来越多,使得核心间的数据移动效率成为制约处理器芯片整体性能的关键因素。光互连技术采用波导方式传输数据,信号传输的损耗低、速度快、延迟小,它通过采用波分复用(WDM)技术可以达到很高的带宽密度,有助于解决片上通信的瓶颈问题。面向未来片上高性能互连的需求,深入分析了电互连技术的现状与局限性,研究并分析了基于硅光子的光互连技术发展现状和趋势,对比了多种典型光互连架构的特点及优缺点,总结了未来硅光子互连技术需要解决的5个重要问题。     

PCI Express中2.5Gbps高速SerDes的设计与实现

PCI Express是当前广泛应用的高速串行传输标准,其V1.0版本提供2.5Gbps的高速传输带宽。对于高速串行传输而言,精确的发送定时与接收同步是其关键技术。本文在详细分析PCI Express物理层技术的基础上,特别针对串行接收端的数据时钟恢复CDR技术展开研究,采用基于锁相环结构的数据时钟恢复技术设计了一款2.5Gbps速率的高速物理层电路,并基于0.13μm CMOS工艺设计了版图实现。基于HSPICE的模拟结果表明,此设计完全满足了PCI Express的要求,其抖动的均方根值为1.51ps,峰峰值为8.14ps。     

A fast transient LED driver with adaptive frequency control according to load variation for large‐sized LCD backlights

A fast transient light‐emitting diode (LED) driver is proposed for large‐sized liquid crystal display TV backlights in attempt to shorten the recovery time and to reduce the voltage fluctuation, while maintaining a high power efficiency. The direct current‐direct current (DC–DC) converter in the proposed LED driver accurately detects the load variation using the dimming data and then adjusts the slew rate and operating frequency according to the detected load variation. Thus, it rapidly controls the turn‐on time of the power switch and then controls the inductor current so that the output of the proposed LED driver can be accurately regulated during the load transient time. To verify the performance of the proposed LED driver, a DC–DC converter and an expandable LED current controller were fabricated using a 0.35‐μm bipolar–complementary metal–oxide–semiconductor (CMOS)–double‐diffused metal–oxide–semiconductor (DMOS) process technology and assembled with 48 LED channels for measurement. The measurement results show that the proposed LED driver improves the recovery time and voltage fluctuation by 45.1% and 45.6%, respectively. In addition, it achieves a maximum power of 115.2 W and a maximum power efficiency of 89.2%. Therefore, the proposed LED driver is suitable for high‐end applications such as large‐sized LED TV backlight modules.     

A CMOS-MEMS mirror with curled-hinge comb drives

A micromirror achieves up to /spl plusmn/4.7/spl deg/ angular displacement with 18 Vdc by a comb-drive design that uses vertical angled offset of the comb fingers. Structures are made from a combination of CMOS interconnect layers and a thick underlying silicon layer. Electrical isolation of the silicon fingers is realized with a slight silicon undercut etch, which disconnects sufficiently narrow pieces of silicon under the CMOS microstructures. The 1 mm by 1 mm micromirror is made of an approximately 40 /spl mu/m-thick single-crystal silicon plate coated with aluminum from the CMOS interconnect stack. The mirror has a peak-to-peak curling of 0.5 /spl mu/m. Fabrication starts with a conventional CMOS process followed by dry-etch micromachining steps. There is no need for wafer bonding and accurate front-to-backside alignment. Such capability has potential applications in biomedical imaging, optical switches, optical scanners, interferometric systems, and vibratory gyroscopes.     

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

An intra‐panel interface addressing all of the high‐speed, low‐power, and low‐electromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4‐Gbps data‐rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power‐saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin‐film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65‐nm and 180‐nm complementary metal‐oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band‐20 and GSM 850 bands. The proposed power‐saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced‐voltage differential signaling interface circuit.     

Actively recharged single photon counting avalanche photodiode integrated in an industrial CMOS process

An actively recharged single photon counting avalanche photodiode (SPAD) is integrated in a conventional CMOS process. A fast recharge through a low impedance path leads to a dead time lower than 10 ns. This outstanding feature allows one to work with pulse repetition rate up to 100 MHz in time correlated single photon counting based experiments. Biased 2.5 V above its breakdown voltage, the 30 μm² sensitive area photodiode has a maximum detection probability of about 20% at λ=440 nm and up to 5% in the visible part of the spectrum. At this bias condition, the dark count rate is as low as 60 Hz at room temperature, making a cooling of the microsystem unnecessary. The AR-SPAD exhibits no afterpulsing phenomenon revealing the maturity of the CMOS process used. The timing resolution of the AR-SPAD is less than 50 ps. For applications where the photons can be focused on the detector with an objective, the AR-SPAD is highly competitive with commercially available single photon counter. Furthermore, CMOS integration opens the way to arrays fabrication as well as co-integration of additional functions to develop smart optical sensors.     

基于功率MOSFET的激光器外触发系统研制

采用功率MOSFET及其驱动器和光纤收发器件,研究了激光触发开关脉冲功率源控制技术中的快上升沿(≤5ns)触发信号产生、驱动、传输及光纤隔离、高耐压脉冲变压器使用等关键技术。给出了激光器外触发控制电路的设计及测试结果,并对其应用特点进行了分析和讨论。     

A 60‐GHz single‐pole‐single‐throw switch in 65‐nm bulk CMOS

A single‐pole‐single‐throw (SPST) switch in a π‐network topology is designed in a 1.2‐V 65‐nm bulk CMOS RF process for millimeter‐wave applications in the 60‐GHz band from 57 to 66 GHz. The SPST switch with an active chip area of only 96 μm × 140 μm achieves the measured 11‐dB return loss, 1.6‐dB insertion loss, and 27.9‐dB isolation at 60 GHz. The SPST switch also shows the simulated power‐handling capability of 11.4 dBm and switching speed of 1 ns at 60 GHz. These results clearly demonstrate that the SPST switch in CMOS rivals the performance of SPST switches in GaAs and therefore has potential to be used in highly‐integrated 60‐GHz CMOS radios. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.