飞腾1500A处理器性能分析工具Likwid研究

在飞腾1500A处理器平台对程序性能分析工具Likwid展开研究,主要研究了飞腾1500A处理器硬件拓扑信息的获取、性能监测单元PMU的访问以及性能分析工具的使用和数据分析。通过hwloc获取飞腾1500A处理器的硬件信息,给程序员提供关于飞腾1500A处理器的拓扑结构及相关概要信息;编写内核驱动模块使能飞腾1500A处理器的性能监控单元,指定事件类型,通过对应硬件计数器记录目标程序执行过程中事件发生的次数;结合简单代码和模板化的微基准测试程序,使用性能分析工具收集程序执行过程中相关数据,进行性能分析。     

一种用于通用处理器结构优化的矩阵乘法性能模型

矩阵乘法作为高性能计算中的关键组成部分,是一种具有计算和访存密集特点的典型应用,因此优化矩阵乘法的性能对通用处理器是非常重要的.为了提高矩阵乘法的性能,本文提出了一种性能模型,用于预测通用处理器上矩阵乘法的执行时间.该模型反映了矩阵乘法执行时间与通用处理器的运算部件、访存带宽、寄存器个数等结构参数之间的关系,可以指导处理器结构的优化来平衡计算和访存能力、提高执行速度.基于该模型本文给出了在一个优化的通用处理器结构中,寄存器个数和访存带宽应满足的理论下界.本文在Godson-3B处理器平台上对该性能模型进行了验证,实验结果表明矩阵乘法执行时间的预测精确度达到95％以上.基于该模型,本文还提出了一种对Godson-3B结构进行优化的方法,使矩阵乘法的执行时间减少了50％左右.     

一类Stencil应用在众核NUMA架构的性能研究

【应用背景】模板计算是CFD（计算流体动力学,Computational Fluid Dynamics）等科学计算的典型算法,其访存性能受到关注。NUMA架构因扩展性好,在以鲲鹏920处理器为代表的ARM架构上普遍被应用。【方法】使用性能分析工具和benchmark程序,对鲲鹏平台的访存和通信子系统进行性能测试。针对典型stencil应用软件CCFD V3.0开展热点分析和性能测试,并建立Roofline模型。【结果】鲲鹏920处理器依托其众核NUMA架构,单节点浮点性能、内存带宽峰值,以及通信时延均优于Intel Xeon E5-2680v2与一款国产处理器。单节点时,CCFD V3.0在鲲鹏平台的运行速度约是Intel平台的2～3倍,是国产处理器的1.5～2倍。【结论】基于ARM架构的鲲鹏平台应用移植简单,其NUMA架构对模板计算一类访存密集性应用具有优势。     

多核处理器片上存储系统研究

针对多核处理器计算能力和访存速度间差异不断增大对多核系统性能提升的制约问题,分析几款典型多核处理器存储系统的设计特点,探讨多核处理器片上存储系统发展的关键技术,包括延迟造成的非一致cache访问、核与cache互连形式对访存性能的束缚以及片上cache设计的复杂化等。     

基于飞腾平台TOE协议栈的设计与实现

传统TCP/IP协议栈要占用大量计算和访存资源,主要表现在中断上下文切换、协议处理和数据拷贝三方面。为减轻飞腾处理器计算负载,逐步采用软硬件一体化即协议卸载引擎（TCP/IP Offload Engine）技术,用硬件部分或全部实现TCP/IP协议处理。因飞腾平台处理器频率较低,网络负载较重时容易成为网络I/O瓶颈。文中对TCP/IP卸载引擎（TOE）技术及其相关原理进行研究,设计并实现了飞腾平台TOE协议卸载引擎的驱动,利用TOE对飞腾平台的网络性能进行优化。测试表明：飞腾平台使用TCP/IP卸载引擎能提高网络吞吐量并减少CPU利用率。     

龙芯3A处理器上FFT的高效实现

FFT(Fast Fourier transform,快速傅立叶变换)是工程应用中的一个基本算法,优化其性能对于推广龙芯系列处理器的应用具有重要意义.本文充分挖掘龙芯3A处理器的硬件特性,对运算量和调整位序的过程作了优化并使用128位访存来减少访存指令的比例,从而实现了高效的FFT算法.实验结果表明,在825M龙芯3A处理器上经过优化后的一维FFT的速度是FF-TW库的2.5倍左右,而二维FFT的速度则是FFTW的3倍左右.     

通用处理器的高带宽访存流水线研究

存储器访问速度的发展远远跟不上处理器运算速度的发展,日益严峻的访存速度问题严重制约了处理器速度的进一步发展.降低load-to-use延迟是提高处理器访存性能的关键,在其他条件确定的情况下,增加访存通路的带宽是降低load-to-use延迟的最有效途径,但增加带宽意味着增加访存通路的硬件逻辑复杂度,势必会增加访存通路的功耗.文中的工作立足于分析程序固有的访存特性,探索高带宽访存流水线的设计和优化空间,分析程序访存行为的规律性,并根据这些规律性给出高带宽访存流水线的低复杂度、低延迟、低功耗解决方案.文中的工作大大简化了高带宽访存流水线的设计,降低了关键路径的时延和功耗,被用于指导Godsonx处理器的访存设计.在处理器整体面积增加1.7%的情况下,将访存流水线的带宽提高了一倍,处理器的整体件能平均提高了8.6%.     

基于Cell多核处理器的层次化运行时支持技术

基于Cell处理器的异构多核架构及软件显式管理的多级存储层次,使其面临编程困难和性能难以有效发挥等问题.现有基于Cell/B.E.的编程模型多侧重于支持类似于流处理的批量访存(bulk data transfer)应用,传统非规则访存应用性能较低.通过扩展Cell/B.E.访存库增强协处理单元的自主作用,以协处理单元为中心建立Cell计算平台上的MPI和弱一致性Pthread分层并行编程运行时支持.分层的运行时支持结构及扩展后的Cell/B.E.访存库使模型具有更好的效率和可扩展性,并且提高了非规则应用的性能;模型中的MPI方便了大量传统并行应用向新架构的移植及开发,而弱一致性Pthread则为MPI提供高效的任务运行时管理支持及为系统级用户提供对架构全面控制的编程接口.实验结果表明,提出的运行时支持技术不仅可适应不同应用的要求,同时借助访存库中的剖分优化机制可有效地挖掘Cell/B.E.架构性能.     

MACT:高通量众核处理器离散访存请求批量处理机制

网络服务等新型高通量应用的迅速兴起给传统处理器设计带来了巨大的挑战.高通量众核处理器作为面向此类应用的新型处理器结构成为研究热点.然而,随着片上处理核数量的剧增,加之高通量应用的数据密集型特点,“存储墙”问题进一步加剧.通过分析高通量应用访存行为,发现此类应用存在着大量的细粒度访存,降低了访存带宽的有效利用率.基于此分析,在高通量处理器设计中通过添加访存请求收集表(memory access collection table,MACT)硬件机制,结合消息式内存机制,用于收集离散的访存请求并进行批量处理.MACT硬件机制的实现,提高了访存带宽的有效利用率,同时也提高了执行效率;并通过时间窗口机制,确保访存请求在最晚期限之前发送出去,保证任务的实时性.实验以典型高通量应用WordCount,TeraSort,Search为基准测试程序.添加MACT硬件机制后,访存数量减少约49％,访存带宽提高约24％,平均执行速度提高约89％.     

存储级并行与处理器微体系结构

随着处理器和主存之间性能差距的不断增大,长延迟访存成为影响处理器性能的主要原因之一.存储级并行通过多个访存并行执行减少长延迟访存对处理器性能的影响.文中回顾了存储级并行出现的背景,介绍了存储级并行的概念及其与处理器性能模型之间的关系;分析了限制处理器存储级并行的主要因素;详细综述了提高处理器存储级并行的各种技术,进行了...     

Task‐based FMM for heterogeneous architectures

High performance fast multipole method is crucial for the numerical simulation of many physical problems. In a previous study, we have shown that task‐based fast multipole method provides the flexibility required to process a wide spectrum of particle distributions efficiently on multicore architectures. In this paper, we now show how such an approach can be extended to fully exploit heterogeneous platforms. For that, we design highly tuned graphics processing unit (GPU) versions of the two dominant operators P2P and M2L) as well as a scheduling strategy that dynamically decides which proportion of subsequent tasks is processed on regular CPU cores and on GPU accelerators. We assess our method with the StarPU runtime system for executing the resulting task flow on an Intel X5650 Nehalem multicore processor possibly enhanced with one, two, or three Nvidia Fermi M2070 or M2090 GPUs (Santa Clara, CA, USA). A detailed experimental study on two 30 million particle distributions (a cube and an ellipsoid) shows that the resulting software consistently achieves high performance across architectures. Copyright © 2015 John Wiley & Sons, Ltd.     

A Case Study on Compiler Optimizations for the Intel® CoreTM 2 Duo Processor

The complexity of modern processors poses increasingly more difficult challenges to software optimization. Modern optimizing compilers have become essential tools for leveraging the power of recent processors by means of high-level optimizations to exploit multi-core platforms and single-instruction-multiple-data (SIMD) instructions, as well as advanced code generation to deal with microarchitectural performance aspects. Using the Intel^® Core^TM 2 Duo processor and Intel Fortran/C++ compiler as a case study, this paper gives a detailed account of the sort of optimizations required to obtain high performance on modern processors.     

SIMD技术与向量数学库研究

首先,结合Intel, AMD和IBM处理器,介绍了单指令流多数据流(SIMD)向量化技术及其各自的特点。其次,在3种平台上对各自开发的函数库中的部分向量数学函数进行了测试。结果表明,相对传统的标量计算,向量化技术带来的加速比较高,特别是Celll SDK函数,因其独特的体系结构,多个向量处理单元带来的平均加速比为10。最后,通过测试结果的对比,发现不同数学库中的向量函数之间在性能方面也存在着差异,并对差异原因进行了分析,得出性能差异主要是处理器架构和向量计算单元个数和访存等因素造成的。     

ARM计算环境下堆芯程序的移植

为了论证国产芯片在堆芯数值计算领域的可行性,对多个堆芯程序在飞腾处理器的ARM通用计算环境中进行了移植,涉及堆芯燃料管理软件的扩散原型程序NACK-R、子通道分析程序CORTH、特征线输运程序OpenMOC和堆芯组件程序KYLIN2。移植过程在ARM计算环境中通过合理的程序代码修订,去除对商业函数库的依赖,且在移植过程中对KYLIN2的特征线循环扫描计算过程引入OpenMP多线程并行,论证单结点多个飞腾处理器核心的并行能力。参照对象Intel商用处理器的频率约为飞腾处理器频率的2倍,堆芯程序移植后的串行运行效率与在Intel计算环境中的串行运行效率差异保持在3~4倍,受限于所使用飞腾处理器型号的缓存大小,部分数据量较大例题的性能差异可能更大。KYLIN2完成多线程并行后计算效率接近在Intel处理器上的串行效率,证明单结点多个飞腾处理器核心能够替换部分堆芯数值计算既有的应用场景。移植结果也表明,混合不同处理器的异构设计,能够在计算资源紧张的情况下充分利用国产硬件,提升计算环境的整体利用效率。     

面向ARM64架构多核微处理器的模板计算性能优化研究

模板计算是一类重要的计算核心,广泛存在于图像和视频处理以及大规模科学和工程计算领域。但是,针对ARM64高性能处理器的模板计算性能的优化研究还很少。为了实现典型模板计算核心在ARM64架构多核微处理器上的并行化和性能优化,基于AMCC X-GENE2和飞腾FT-1500A多核微处理器特点,提出了基于两维度绑定的优化方法,该方法通过线程与CPU绑定以及线程与数据块绑定,减少了线程调度的并行开销,增加了Cache的命中率。实验结果表明,该方法提升了模板计算在ARM64架构多核微处理器上的性能,且在两种ARM64架构多核微处理器平台上都表现出较好的可扩展性。     

80C196KC与ADC接口设计及可靠性分析

主要介绍80C196KC及MAX120的功能特点和使用方法,详细叙述了80C196KC与MAX- IM12-bitA/D转换器MAX120接口电路的硬件设计;给出MCS-96汇编语言实现方法;分析说明实际设计中提高系统工作可靠性的方法。     

Hyperthreading technology in the netburst microarchitecture

Hyperthreading technology, which brings the concept of simultaneous multithreading to the Intel architecture, was first introduced on the Intel Xeon processor in early 2002 for the server market. In November 2002, Intel launched the technology on the Intel Pentium 4 at clock frequencies of 3.06 GHz and higher, making the technology widely available to the consumer market. This technology signals a new direction in microarchitecture development and fundamentally changes the cost-benefit tradeoffs of microarchitecture design choices. This article describes how the technology works, that is, how we make a single physical processor appear as multiple logical processors to operating systems and software. We highlight the additional structures and die area needed to implement the technology and discuss the fundamental ideas behind the technology and why we can get a 25-percent boost in performance from a technology that costs less than 5 percent in added die area. We illustrate the importance of choosing the right sharing policy for each shared resource by describing, examining, and comparing three different sharing policies: partitioned resources, threshold sharing, and full sharing. The choice of policy depends on the traffic pattern, complexity and size of the resource, potential deadlock/livelock scenarios, and other considerations. Finally, we show how this technology significantly improves performance on several relevant workloads.     

How many cores do we need to run a parallel workload: A test drive of the Intel SCC platform?

As semiconductor manufacturing technology continues to improve, it is possible to integrate more and more transistors onto a single processor. Many-core processor design has resulted in part from the search to utilize this enormous transistor real estate. The Single-Chip Cloud Computer (SCC) is an experimental many-core processor created by Intel Labs. In this paper we present a study in which we analyze this innovative many-core system by running several workloads with distinctive parallelism characteristics. We investigate the effect on system performance by monitoring specific hardware performance counters. Then, we experiment on varying different hardware configuration parameters such as number of cores, clock frequency and voltage levels. We execute the chosen workloads and collect the timing, power consumption and energy consumption information on such a many-core research platform. Thus, we can comprehensively analyze the behavior and scalability of the Intel SCC system with the introduced workload in terms of performance and energy consumption. Our results show that the profiled parallel workload execution has a communication bottleneck on the Intel SCC system. Moreover, our results indicate that we should carefully choose the number of cores to execute different workloads in order to yield a balance between execution performance and energy efficiency for different applications.     

Multiprocessors should support simple memory consistency models

In the future, many computers will contain multiple processors, in part because the marginal cost of adding a few additional processors is so low that only minimal performance gain is needed to make the additional processors cost effective. Intel, for example, now makes cards containing four Pentium Pro processors that can easily be incorporated into a system. Multiple processor cards like Intel's will help multiprocessing spread from servers to the desktop. But how will these multiprocessors be programmed? The evolution of the programming model is already under way. One important function of the programming model is to describe how memory operates. For a multiprocessor, a reasonable model is sequential consistency (SC), which makes a multiprocessor behave like a multitasking uniprocessor. Nevertheless, many commercial multiprocessors support more relaxed memory models. The author argues that multiprocessors should support SC because-with speculative execution, relaxed models do not provide sufficient additional performance to justify exposing their complexity to the authors of low level software