C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

Post-stress interface trap generation induced by oxide-field stresswith FN injection

Interface trap generation in nMOS transistors during both stressing and post-stress periods under the conditions of oxide field (dynamic and dc) stress with FN injection is investigated with charge pumping technique. In contrast to the post-stress interface trap generation induced by hot carrier stress which is a logarithmical function of post-stress time, the post-stress interface trap generation induced by oxide-field stress with FN injection first increases with post-stress time but then becomes saturated. The mechanisms for the interface trap generation in both stressing and post-stress periods are described     

The Impact of Nitrogen Engineering in Silicon Oxynitride Gate Dielectric on Negative-Bias Temperature Instability of p-MOSFETs: A Study by Ultrafast On-The-Fly $I_{rm DLIN}$ Technique

Degradation of p-MOSFET parameters during negative-bias temperature instability (NBTI) stress is studied for different nitridation conditions of the silicon oxynitride (SiON) gate dielectric, using a recently developed ultrafast on-the-fly I_DLIN technique having 1-mus resolution. It is shown that the degradation magnitude, as well as its time, temperature, and field dependence, is governed by nitrogen (N) density at the Si/SiON interface. The relative contribution of interface trap generation and hole trapping to overall degradation as varying interfacial N density is qualitatively discussed. Plasma oxynitride films having low interfacial N density show interface trap dominated degradation, whereas relative hole trapping contribution increases for thermal oxynitride films having high N density at the Si/SiON interface.     

Reversible and irreversible interface trap centres generated at high electric fields in MOS structures

In this work, we present results of the study of interface trap generation processes at the Si–SiO₂ interface in MOSFET structures caused by high oxide field stress. Changes in areal density and energy distribution in the Si band gap of the interface traps were monitored using the II-level conventional charge pumping technique. The generated interface traps were divided into two types: reversible and irreversible in relation to their discharge by low field electron injection. A broad presentation of changes in density and energy distribution of the interface traps was included. The threshold value of oxide field for interface trap generation was obtained.     

Analysis of trap effect on reliability using the charge pumping technology in La-incorporated high-k dielectrics

In this paper, reliability characteristics of nMOSFETs with La-incorporated HfSiON and HfON and metal gate have been studied. HfLaSiON shows greater device degradation by hot carrier (HC) stress than by positive bias temperature (PBT) stress, while HfLaON exhibits similar degradation during HC stress and PBT stress. To evaluate the contribution of bulk trap during PBT stress, a novel charge pumping (CP) technique is applied to extract the distribution of bulk trap (N_bt) before and after PBT stress. To evaluate permanent damage during HC stress, an appropriate selection of frequency range in CP method is considered. The initial interface trap density of HfLaSiON and HfLaON is similar, while the near-interface trap (N_IT) density of HfLaSiON after HC stress is equal or greater than that of HfLaON.     

FORWARD GATED—DIODE METHOD FOR EXTRACTING HOT—CARRIER—STRESS0INDUCED BACK INTERFACE TRAPS IN SOI／NMOSFETs

The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained.     

Application of forward gated-diode R–G current method in extracting F–N stress-induced interface traps in SOI NMOSFETs

Application of the forward gated-diode recombination–generation (R–G) current method in extracting the F–N stress-induced interface traps in SOI NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method can directly give F–N stress-induced interface trap density from the measured R–G current peak of the gated-diode architecture. An expected power law relationship between the induced interface trap density and the accumulated stress time has been obtained. For the different stress time and the bias voltage, the stress experiments demonstrate the induced interface traps increase in a similar power law factor, 0.4, revealing the same generation mechanism of the interface traps.     

Evaluation of NBTI in HfO/sub 2/ gate-dielectric stacks with tungsten gates

Negative-bias temperature instability (NBTI) of the threshold voltage in ultrathin HfO/sub 2/ p-type field-effect transistors (pFET) with tungsten gates is reported. The dependence of threshold voltage, transconductance peak, and interface trap density on stress time is investigated for various negative stress voltages and temperatures. The measurements show that the threshold voltage shifts with a concomitant decrease in transconductance peak and increase in interface trap density as assessed by subthreshold slope and dc current-voltage (DCIV) method. The threshold voltage shift data are fitted with a stretched exponential equation and the fits are used for estimating lifetime. The measurements show that NBTI-related degradation in HfO/sub 2/ stacks is comparable to that observed in SiO/sub 2//poly Si pFETs.     

Effects of Fowler-Nordheim stress on interface trap density andemission cross sections in n-MOSFETs studied by three-level chargepumping

High field Fowler-Nordheim (F-N) stress effects on interface-trap density and emission cross sections in n-MOSFETs have been studied using three-level charge pumping (3LCP). The results show that 3LCP is sensitive to changes in trap cross section as a function of energy in the bandgap. An asymmetric change in electron and hole emission cross sections following F-N tunneling injection is found. The work also provides further insight into the influence of hot electrons on interface trap generation in MOSFETs in both the upper and lower bandgap following electrical stress     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Trapped charge distributions in thin (10 nm) SiO2 filmssubjected to static and dynamic stresses

Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models     

Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current–voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction–diffusion (R–D) model and with an assumption that additional interface traps$(N_ it^ast)$are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the$hboxSiO_2/hboxSi$interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si–H bonds at the beginning of the stressing phase in each cycle. Hence,$N_ it^ast$depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R–D model.     

Gold traps in 〈100〉 silicon-silicon dioxide interfaces

The effects of gold on the trapping states at the silicon-silicon dioxide interface have been studied. A theory is presented which allows the ‘static’ low frequency C-V characteristic of a MOS capacitor, with arbitrary interface trap distribution, to be determined. The quasi-static technique of Kuhn, which measures the displacement current response to a slowly varying linear voltage, is subsequently used to obtain experimental curves which are correlated with theory. It is found that at low temperatures (? 230°K) the technique resolves pronounced structure in the interfacial trap distribution that is not apparent at room temperature.To assess the effects of varying amounts of gold, various diffusion times at 900°C were used on n-type silicon wafers of (100) orientation. It was found that interface trap density increased with extended diffusion time, but the energy distribution remained essentially the same, exhibiting pronounced maxima at energies E_v + 0.36 eV and E_v + 0.63 eV. As well as producing peaks in the distribution, the gold diffusions resulted in an increase in interface state density by approximately a factor of 5 from the control devices.     

Slow transients in polyimide-passivated InP-InGaAs HBTs: effects of UV irradiation, thermal annealing and electrical stress

The effects of UV irradiation, thermal annealing and electrical bias on the base current instability in polyimide (PI)-passivated InP-based heterojunction bipolar transistors (HBTs) have been studied. The base current transient could be effectively suppressed by UV irradiation. The suppression of current transient by UV irradiation can be attributed to the reduction of the near interface trap density in the PI, which has long-term stability at room temperature. However, baking the device at a temperature higher than 100 /spl deg/C may induce a significant increase in PI trap density as well as the broadening of spatial electron trap distribution causing the enhancement of current transient, and the current transient induced by electrical stress could be directly related to the device self-heating through thermal annealing effect.     

In-depth exploration of Si-SiO2 interface traps in MOStransistors using the charge pumping technique

It is shown that the charge pumping (CP) technique can be used for extraction of the depth concentration profile of traps situated in the oxide of metal-oxide-semiconductor (MOS) transistors, near and at the Si-SiO₂ interface. The trap density is obtained from the variation of the charge pumping current as a function of frequency, the other measurement parameters being kept constant. The concentration profiles are measured on n and p-channel transistors from several technologies, and on virgin and stressed devices. The results show that the trap concentration decreases rapidly from the Si-SiO₂ interface in the direction of the oxide depth and suggest that it becomes constant at a fraction of a nanometer from the silicon interface. The method easily demonstrates the trap creation due to Fowler-Nordheim stress. The profiles compare favorably with those measured using a new drain-current transient technique. In all cases, the integration of the depth concentration profiles leads to the interface trap densities measured using the conventional charge pumping method     

Determination of interface and bulk traps in the subthreshold region of polycrystalline silicon thin-film transistors

A simple method to determine the Interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. The energy distribution of the interface trap density has been extracted from analysis of the transfer characteristics in the subthreshold region of operation. Using the obtained interface state distribution, the energy distribution of the bulk traps has been determined by fitting the surface potential at each gate voltage with an analytical theoretical model. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gap and band-tails with density increasing exponentially with the energy when the trap energy approaches the conduction band-edge.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

A novel subthreshold slope technique for the extraction of theburied-oxide interface trap density in the fully depleted SOIMOSFET

A novel experimental technique, based on the double-gate operation, is proposed for extracting the back interface trap density of the fully depleted SOI MOSFET. The method relies on simple current-voltage measurements, requires no prior knowledge of the silicon film thickness, and successfully eliminates inaccuracies arising from thickness variations of the accumulation layer, by maintaining both interfaces in depletion. The sensitivity of the technique is shown to depend on the ratio of the interface trap and oxide capacitances of the buried oxide, and is thus limited only by the buried oxide thickness. The technique has been successfully used to monitor the increase in back interface trap density following Fowler-Nordheim stress     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.