A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A 256-kbit flash E/SUP 2/PROM using triple-polysilicon technology

A high-density 256-kb flash electrically erasable PROM (E/SUP 2/PROM) with a single transistor per bit has been developed by utilizing triple-polysilicon technology. As a result of achieving a novel compact cell that is as small as 8/spl times/8 /spl mu/m/SUP 2/, even with relatively conservative 2.0-/spl mu/m design rules, a small die size of 5.69/spl times/5.78 mm/SUP 2/ is realized. This flash E/SUP 2/PROM is fully pin-compatible with a 256-kb UV-EPROM without increasing the number of input pins for erasing by introducing a novel programming and erasing scheme. Programming time is as fast as 200 /spl mu/s/byte and erasing time is less than 100 ms per chip. A typical access time of 90 ns is achieved by using sense-amplifier circuitry.     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.     

A DPS array with programmable resolution and reconfigurable conversion time

A CMOS digital pixel sensor (DPS) with programmable resolution and reconfigurable conversion time is described. The chip features a unique architecture based on the pulse width modulation (PWM) technique and operates with either an 8-b or 4-b accuracy. The 8-b conversion mode is used for high-precision imaging while the 4-b conversion mode provides a shorter conversion time and a two times increase in spatial resolution. Two quantization schemes are studied, namely, the uniform and the nonuniform time-domain quantizers, which are referred to as UQ and NUQ, respectively. It is shown that the latter scheme not only permits to linearize the nonlinear response of the PWM sensor, but also allows to significantly speed up the conversion time, particularly for wide dynamic range and low coding resolutions. A prototype of 32/spl times/32/64/spl times/32 pixels has been fabricated using 1-poly, 5-metal CMOS 0.35-/spl mu/m n-well standard process. Power dissipation is 10 mW at V/sub DD/=3.3 V, dynamic range is 90 dB, while dark current was measured at 1 pA. The reconfiguration features of the chip have been verified experimentally.     

New radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithms for 3-D DFT

In this paper, new three-dimensional (3-D) radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithms are developed and their implementation schemes discussed. The algorithms are developed by introducing the radix-2/4 and radix-2/8 approaches in the computation of the 3-D DFT using the Kronecker product and appropriate index mappings. The butterflies of the proposed algorithms are characterized by simple closed-form expressions facilitating easy software or hardware implementations of the algorithms. Comparisons between the proposed algorithms and the existing 3-D radix-(2/spl times/2/spl times/2) FFT algorithm are carried out showing that significant savings in terms of the number of arithmetic operations, data transfers, and twiddle factor evaluations or accesses to the lookup table can be achieved using the radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) DIF FFT algorithm over the radix-(2/spl times/2/spl times/2) FFT algorithm. It is also established that further savings can be achieved by using the radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithm.     

Pulse frequency modulation based CMOS image sensor for subretinal stimulation

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16/spl times/16 pixels. Biphasic current stimulus pulses at above threshold levels of the human retina (500 /spl mu/A) at varying frame rates (4 Hz to 8 kHz) have been achieved. The implant chip was fabricated using standard CMOS technology.     

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.     

An Integrated Systolic Array Design for Video Compression

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. These functions are the prime components in video compression and take a great amount of computation. To meet the real-time application requirements, many systolic array architectures are proposed for individually performing one of those functions. However, these functions contain similar computational procedure. The matrix-vector product forms of the three functions are quite analogous. After extracting the common computation component, we design an integrated one-dimensional systolic array that can perform aforementioned three functions. The proposed architecture can efficiently perform three typical functions: (1) the full-search block matching with block of size 16 × 16 and the search are from –8 to 7; (2) the 2-D 2 level Harr transform with block of size 8 × 8; and (3) the full-search vector quantization with input vector of size 2 × 2. A utilization rate of 100% to 97% is achieved in the course of executing full-search block matching and full-search vector quantization. When it comes to perform 2-D discrete wavelet transform, the utilization rate is about 32%. The proposed integrated architecture has lowered hardware cost and reduced hardware structure. It befits the VLSI implementation for video/image compression applications.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

A 70-ns word-wide 1-Mbit ROM with on-chip error-correction circuits

A 1-Mb ROM has been developed, organized as either 64K/spl times/16 or 128K/spl times/8 in a pin-selectable option. Multiplexing the address inputs and the data outputs onto the same pins makes it possible to fit into a 28-pin package and to perform straightforward interfacing with some popular 16-bit microprocessors. The process technology is a 1.5-/spl mu/m twin-well double-level-metal CMOS on a grounded p-type substrate. The device uses some dynamic circuitry during the start of the active cycle, but automatically takes itself back into the static precharge state-except for the latched outputs. Typical access time is 70 ns. New high-speed error detection and correction circuits were developed which work in about 10 ns. Because all 16 outputs are not driven at once, but half are delayed by about 15 ns through a process-tracking delay circuit, the on-chip error correction is finished before the process-tracking delay circuit is through, and error correction costs no further access penalty. These error correction circuits enhance both yield and reliability.     

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

Design of a single-chip digital lattice equalizer filter

One lattice equalizer stage is designed on a single chip using 4-/spl mu/m NMOS technology. All the arithmetic operations of the chip are performed bit-serially under the control of a global two-phase clock, and they are totally pipelined. The data are represented as 16-bit two's complement fixed-point numbers. A built-in test scheme allows the offline testing of the chip with high fault coverage at a minimal hardware overhead. Direct coupling between chips permits the realization of filters of higher order. In addition, the structure of the lattice equalizer permits the use of the same chip in linear prediction problems. SPICE simulation results and fabrication of the major blocks in the design demonstrated that operating clock frequencies of up to 8 MHz are possible. At the maximum estimated operating clock frequency, the chip can accommodate applications with data rates of up to 500 kHz.     

A 4-Mbit CMOS EPROM

A high-density (512K-word/spl times/8-b) erasable programmable read-only memory (EPROM) has been designed and fabricated by using 0.8-/spl mu/m n-well CMOS technology. A novel chip layout and a sense-amplifier circuit produce a 120-ns access time and a 4-mA operational supply current. The interpoly dielectric, composed of a triple-layer structure, realizes a 10-/spl mu/s/byte fast programming time, in spite of scaling the programming voltage V/SUB PP/ from 12.5 V for a 1-Mb EPROM to 10.5 V for this 4-Mb EPROM. To meet the increasing demand for a one-time programmable (OTP) ROM, a circuit is implemented to monitor the access time after the assembly. A novel redundancy scheme is incorporated to reduce additional tests after the laser fuse programming. Cell size and chip size are 3.1/spl times/2.9 /spl mu/m/SUP 2/ and 5.86/spl times/14.92 mm/SUP 2/, respectively.     

A signal-processing CMOS image sensor using a simple analog operation

We have developed a high-density CMOS image sensor with a normal mode and three signal-processing function modes: wide dynamic-range mode, motion-detection mode, and edge-extraction mode. Small pixel size and real-time operation are achieved by using a four-transistor and one-capacitor pixel scheme and column-parallel on-chip analog operation. The chip includes 512 (H) /spl times/384 (V) effective pixels. Each pixel has a sufficient fill factor of 24% in an area of 9.3/spl times/9.3 /spl mu/m/sup 2/. The dynamic range at the wide dynamic-range mode is a maximum 97 dB against 51 dB at the normal-readout mode. The chip consumes 79 mW, and the gain-control amplifier and 8-b analog-to-digital converter operate at 46 frames/s using a 3.3-V single power supply.     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.     

A 32-bit execution unit in an advanced NMOS technology

The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations and has an on-chip control ROM for instruction decoding. It operates with a single 5-V supply voltage. Measurements resulted in a typical power dissipation of 750 mW and a maximum operation frequency of 6.5 MHz. At this frequency a 32/spl times/32 bit multiplication is performed in less than 5.5 /spl mu/s.     

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

An AND-type match-line scheme for high-performance energy-efficient content addressable memories

High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 /spl times/ 128-b CAM macro, based on a 0.18-/spl mu/m 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 /spl times/ 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.