A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-$Q$ Above-IC Inductors

A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-$Q$ above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high- $Q$ above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input 1 dB compression point $({rm IP}_{{-}1~{rm dB}})$ is ${- 9.5}~{rm dBm}$ and the input referred third-order intercept point $(P _{rm IIP3})$ is ${+ 2.25}~{rm dBm}$. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for RF ICs above 20 GHz.      

Wideband LNA Compatible for Differential and Single-Ended Inputs

This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 $mu{rm m}$ CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, ${+ 1}~{rm dBm}$ IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, ${- 0.5}~{rm dBm}$ IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 ${rm mm}^{2}$.      

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.      

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

W-Band Active Down-Conversion Mixer in Bulk CMOS

A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.      

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ${sim}2$ nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient $S_{11}$ is below ${-}13.0$ dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ${sim}40$ fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ${sim}100$ V/fF) among the published results for RF LNA applications.      

Analysis and Design of a CMOS UWB LNA With Dual- -Branch Wideband Input Matching Network

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt–shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel $RLC$-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves ${ S}_{11}$ below $-$8.6 dB, ${ S}_{22}$ below $-$10 dB, ${ S}_{12}$ below $-$26 dB, flat ${ S}_{21}$ of 12.26 $pm$ 0.63 dB, and flat NF of 4.24 $ pm$ 0.5 dB over the 3.1–10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only $pm$22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

A 2.4-GHz Resistive Feedback LNA in 0.13-$mu$m CMOS

A $g_{m}$-boosted resistive feedback low-noise amplifier (LNA) using a series inductor matching network and its application to a 2.4 GHz LNA is presented. While keeping the advantage of easy and reliable input matching of a resistive feedback topology, it takes an extra advantage of $g_{m}$ -boosting as in inductively degenerated topology. The gain of the LNA increases by the $Q$ -factor of the series RLC input network, and its noise figure (NF) is reduced by a similar factor. By exploiting the $g_{m}$-boosting property, the proposed fully integrated LNA achieves a noise figure of 2.0 dB, S21 of 24 dB, and IIP3 of ${- 11}~ hbox{dBm}$ while consuming 2.6 mW from a 1.2 V supply, and occupies 0.6 ${hbox {mm}}^{2}$ in 0.13-$mu{hbox {m}}$ CMOS, which provides the best figure of merit. This paper also includes an LNA of the same topology with an external input matching network which has an NF of 1.2 dB.      

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

Multi-Standard Mobile Broadcast Receiver LNA With Integrated Selectivity and Novel Wideband Impedance Matching Technique

A CMOS LNA supporting multiple mobile video standards (MediaFLO, DVB-H, and ISDB-T) is implemented using a 0.18 $ mu$m CMOS process. The LNA uses a novel feedback configuration and implements an RF elliptic low-pass filter (LPF) response. Because of this elliptic LPF response, the receiver is able to operate concurrently with radio transmitter leakage from GSM, DCS, WLAN, and Bluetooth. The design decouples the feedback path from the main path to allow integration of the LPF as well as obtain wideband input matching. Measurement results show voltage gain of 25 dB, NF of 1.6 dB, and IIP3 of ${-}$2 dBm in MediaFLO mode. DVB-H mode demonstrates voltage gain of 25 dB, NF of 1.8 dB, and IIP3 of ${-}$1 dBm while achieving interference rejection greater than 70 dB.      

Analysis, Design, and $X$-Band Implementation of a Self-Biased Active Feedback $G_{m}$ -Boosted Common-Gate CMOS LNA

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for $g_{m}$ boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without $g_{m}$ boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-$mu$ m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of ${-}$ 11.3 dBm, a return loss of ${-}$ 17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 $mu$m $^{2}$.      

A 3–10 GHz CMOS UWB Low-Noise Amplifier With ESD Protection Circuits

A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protection circuit for ultra-wide band (UWB) applications is presented. With the use of a common-gate scheme with a ${rm g}_{rm m}$ -boosted technique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combination of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss $({rm S}_{11})$ and output return loss $({rm S}_{22})$ are less than ${-}8.3$ dB and ${-}9$ dB, respectively. The measured power gain $({rm S}_{21})$ is $11 pm 1.5$ dB, and the measured minimum NF is 3.3 dB at 4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm$,times,$ 0.73 mm.      

A Biphase Modulator Circuit for Impulse Radio-UWB Applications

This letter presents a circuit to provide binary phase shift keying to ultra-wideband (UWB) impulse transmitters. The circuit is based on a Gilbert-cell multiplier and uses active on-chip balun and unbalanced-to-balanced converters for single-ended to single-ended operation. Detailed measurements of the circuit show a gain ripple of $pm 1~{rm dB}$ at an overall gain of $-2~{rm dB}$, an input reflection below $-12~{rm dB}$, an output reflection below $-18~{rm dB}$, a group delay variation below 6 ps and a $-1~{rm dB}$ input compression point of more than 1 dBm in both switching states over the full 3.1–10.6 GHz UWB frequency range. A time domain measurement verifies the switching operation using an FCC-compliant impulse generator. The circuit is fabricated in a $0.8~mu {rm m}$ Si/SiGe HBT technology, consumes 31.4 mA at a 3.2 V supply and has a size of $510 times 490~mu{rm m}^{2}$ , including pads. It can be used in UWB systems using pulse correlation reception or spectral spreading.      

A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters

Low-distortion I/Q baseband filters interface with a 2.5 GHz RF receiver front-end configured as a Gm-cell in a direct-conversion architecture targeted towards WLAN 802.11b application. The active I/Q current-mode filters use AC current to carry the large swing of both desired and blocker signals, relaxing the voltage headroom requirement to a 1.2 V supply. An on chip master–slave automatic tuner is used to lock the filter bandwidth to a precision 20 MHz reference crystal oscillator, resulting in a $≪ ,$3% tuning accuracy and $≪, $ 0.5% I/Q bandwidth matching. The receiver achieves a 3.2 dB DSB NF, ${-}$14 dBm out-of-band IIP3, and ${+}$ 27 dBm worst case IIP2, all referred to the LNA input, while drawing 30mA from a 2.7 V supply. The chip is fabricated in a 0.5 $mu$m 46 GHz $f_{T}$ SiGe BiCMOS process. The active area is 2.54 mm$^{2}$ .      

A 0.1–5 GHz Cryogenic SiGe MMIC LNA

In this letter, the design and measurement of the first SiGe integrated-circuit LNA specifically designed for operation at cryogenic temperatures is presented. At room temperature, the circuit provides greater than 25.8 dB of gain with an average noise temperature $(T_{e})$ of 76 K $(NF=1 {rm dB})$ and $S_{11}$ of $-$ 9 dB for frequencies in the 0.1–5 GHz band. At 15 K, the amplifier has greater than 29.6 dB of gain with an average $T_{e}$ of 4.3 K and $S_{11}$ of $-$14.6 dB for frequencies in the 0.1–5 GHz range. To the authors' knowledge, this is the lowest noise ever reported for a silicon integrated circuit operating in the low microwave range and the first matched wideband cryogenic integrated circuit LNA that covers frequencies as low as 0.1 GHz.