CMOS current-mode pseudo-exponential function circuit

A current-mode analogue circuit that implements a pseudo-exponential function is proposed. The design of the circuit is based on Taylor's series approximation, using MOS transistors in the saturation region. The advantage of this circuit is that the output current presents a very low temperature coefficient (TC) and is also immune to the body-effect. Simulation and experimental results show that the circuit offers a maximum output range of ~30 dB, with an error of less than 1 dB and TC=-233 ppm/°C     

Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS

A new current-mode CMOS algorithmic analogue-to-quaternary data convertor circuit has been realised in a standard polysilicon-gate CMOS technology. This circuit accepts an analogue current input and develops a set of quaternary, base-four, output currents. A single type of convertor cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits.<>     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

A CMOS current-mode squaring circuit free of error resulting from carrier mobility reduction

This paper presents a new current-mode squaring circuit. The design is based on MOSFETs translinear principle in strong inversion. A new compensation technique to minimize the second order effects caused by carrier mobility reduction in short channel MOSFETs is proposed. Tanner T-spice simulation tool is used to confirm the functionality of the proposed design in 0.18 µm CMOS process technology. Simulation results indicate that the maximum linearity error is 1.2 %; power consumption is 326 µW and bandwidth of 340 MHz.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Compact current-mode loser-take-all circuit

A CMOS circuit is presented that takes an array of analogue input currents and generates an array of binary output voltages in which the output corresponding to the minimum input current is high and all other outputs are low. This loser-take-all circuit also encodes the minimum current as a voltage that is distributed to all elements through a global wire. Because transistors operate in the subthreshold regime, a single compact cell implemented with as few as two transistors per cell dissipates power in the microwatt range. A three-cell loser-take-all circuit was fabricated using a MOSIS 2 μm p-well process, and experimental data are presented     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

CMOS current-mode exponential-control variable-gain amplifier

A CMOS current-mode exponential-control variable-gain amplifier is presented. It consists of a first-order current-mode pseudo-exponential circuit and a current-mode multiplier. Based on the Taylor's series expansion, the pseudo-exponential circuit can be realised by MOSFETs in saturation. The proposed circuit has been fabricated in a 0.5 μm n-well CMOS process with a gain control range of 15 dB. The experimental results confirm the feasibility of the proposed variable-gain amplifier     

Fully balanced CMOS current-mode circuits

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V_dd 5 V     

Low-voltage CMOS current-mode exponential circuit with 70 dB output dynamic range

The paper proposes new accurate exponential circuits, having a multitude of practical applications in analog signal processing. The original method for obtaining the exponential function is based on the utilization of new superior-order approximation functions. The accuracy of the proposed structures is excellent and the output dynamic range is strongly extended as a result of the fourth-order approximation and of the independence of implemented function on technological errors and on temperature variations (the best original proposed architecture of the exponential generator has an output dynamic range of 70 dB for an approximation error smaller than ±1 dB). The exponential circuits are designed for implementing in 0.18 µm CMOS technology, having a low-voltage operation (a minimal supply voltage of 1 V). The power consumptions of the proposed exponential circuits are smaller than 0.08 mW, for a supply voltage of 1 V. As application of the new exponential circuit, a dB-linear VGA circuit with high output dynamic range will be presented. The new computational structures have the possibility of generating any continuous mathematical function, presenting also an increased modularity and controllability and reduced design costs per implemented function.     

A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques

This paper presents a new high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves speed up to 45% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, two other structures have been chosen and all of the circuits have been simulated in 0.18 μm standard TSMC CMOS process with 1.8 V power supply voltage.     

SIMPLIFICATION OF CURRENT-MODE MULTIVALUED CMOS CIRCUITS

This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).     

A flexible logic circuit based on a MOS-NDR transistor in standard CMOS technology

A MOS-NDR (negative differential resistance) transistor which is composed of four n-channel metaloxide-semiconductor field effect transistors (nMOSFETs) is fabricated in standard 0.35 μm CMOS technology.This device exhibits NDR similar to conventional NDR devices such as the compound material based RTD (resonant tunneling diode) in current-voltage characteristics.At the same time it can realize a modulation effect by the third terminal.Based on the MOS-NDR transistor,a flexible logic circuit is realized in this work,which can transfer from the NAND gate to the NOR gate by suitably changing the threshold voltage of the MOS-NDR transistor.It turns out that MOSNDR based circuits have the advantages of improved circuit compaction and reduced process complexity due to using the standard IC design and fabrication procedure.     

基于标准CMOS工艺制作的MOS-NDR柔性逻辑电路

本文利用0.35um标准CMOS工艺实现了一种由4个nMOSFET构成的MOS型负阻器件。这种负阻器件的I-V特性与传统的化合物材料构成的共振隧穿二极管（RTD）的特性类似,而且可以通过第三端来调制其I-V特性。基于这种MOS型负阻器件,本文实现了一种通过调节阈值电压来实现与非门（NAND）到或非门（NOR）转变的柔性逻辑电路。此种电路所用器件较少,而且由于使用标准IC的设计和工艺流程,制作工艺大大简化。     

CMOS current-mode divider and its applications

Compact, accurate and low-power analog CMOS circuits for current-mode division and pseudo-exponential function generation are presented, based on a new variable transresistance amplifier. Experimental results of the circuits fabricated in a 0.5-/spl mu/m 2P2M n-well CMOS process show better than 0.3% total harmonic distortion. Measured power is less than 0.22 mW at 100-MHz bandwidth and /spl plusmn/1.5-V supply voltages.     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

High-performance current-mode instrumentation amplifier circuit

A high-performance current-mode instrumentation amplifier circuit is described in this paper. It has a high common mode rejection ratio, high gain, high accuracy, wide bandwidth and bandwidth gain-independence. It utilizes commercially available integrated circuits and is easily implemented. Experimental results show that at low frequencies a common mode rejection ratio of 120 dB is attainable.