Organic Field‐Effect Transistor Memory Devices Using Discrete Ferritin Nanoparticle‐Based Gate Dielectrics

Organic field‐effect transistor (OFET) memory devices made using highly stable iron‐storage protein nanoparticle (NP) multilayers and pentacene semiconductor materials are introduced. These transistor memory devices have nonvolatile memory properties that cause reversible shifts in the threshold voltage (V_th) as a result of charge trapping and detrapping in the protein NP (i.e., the ferritin NP with a ferrihydrite phosphate core) gate dielectric layers rather than the metallic NP layers employed in conventional OFET memory devices. The protein NP‐based OFET memory devices exhibit good programmable memory properties, namely, large memory window ΔV_th (greater than 20 V), a fast switching speed (10 μs), high ON/OFF current ratio (above 10⁴), and good electrical reliability. The memory performance of the devices is significantly enhanced by molecular‐level manipulation of the protein NP layers, and various biomaterials with heme Fe^III/Fe^II redox couples similar to a ferrihydrite phosphate core are also employed as charge storage dielectrics. Furthermore, when these protein NP multilayers are deposited onto poly(ethylene naphthalate) substrates coated with an indium tin oxide gate electrode and a 50‐nm‐thick high‐k Al₂O₃ gate dielectric layer, the approach is effectively extended to flexible protein transistor memory devices that have good electrical performance within a range of low operating voltages (<10 V) and reliable mechanical bending stability.     

Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal–oxide–semiconductor (CMOS)‐compatible Ti/SiN_x/p⁺‐Si memristor by simply reducing the cell size down to sub‐100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub‐100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low‐resistance state is attributed to Fowler–Nordheim tunneling dominating in the high‐voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal–nitride–silicon memristor device paves the way to realize CMOS‐compatible high‐density crosspoint array applications.     

A fully tunable single-walled carbon nanotube diode

We demonstrate a fully tunable diode structure utilizing a fully suspended single-walled carbon nanotube. The diode's turn-on voltage under forward bias can be continuously tuned up to 4.3 V by controlling gate voltages, which is ～6 times the nanotube band gap energy. Furthermore, the same device design can be configured into a backward diode by tuning the band-to-band tunneling current with gate voltages. A nanotube backward diode is demonstrated for the first time with nonlinearity exceeding the ideal diode. These results suggest that a tunable nanotube diode can be a unique building block for developing next generation programmable nanoelectronic logic and integrated circuits.     

Wavy Architecture Thin‐Film Transistor for Ultrahigh Resolution Flexible Displays

A novel wavy‐shaped thin‐film‐transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn‐on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)‐based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low‐power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.     

Evaluation of a Non‐destructive High‐voltage Technique for the Detection of Pinhole Leaks in Flexible and Semi‐rigid Packages for Foods

This study evaluated the capabilities of a high‐voltage technique for the detection of pinhole leaks by using flexible pouches and semi‐rigid cups for foods. This evaluation was performed by measuring the discharge voltage when high voltages ranging from 0.25 to 10 kV were applied to sample packages. The results showed that package contact surface area, film thickness, food type and electrical conductivity are significant factors affecting the detection of pinhole leaks in flexible pouches by a high‐voltage leak detection (HVLD) system within the ranges tested (p < 0.05). For plastic cups with plastic‐laminated and foil‐laminated lids, the headspace inside a cup had the greatest effect followed by dielectric constant of lid films, electrical conductivity of foods and pinhole diameter (p < 0.01). In general, the HVLD system can detect pinholes as small as 10 µm in both plastic‐laminated and foil‐laminated pouches and lid cups, even at worst‐case scenario conditions, including liquid, semi‐solid and solid foods with 0.85 a_w. Because of high voltages applied, however, delamination in foil‐laminated films occurred when an applied voltage was greater than 3.5 kV, which resulted in increased oxygen permeability. Statistical z‐test analysis of results from blind studies showed that the HVLD technique is significantly effective in determining defective pouches and cups with pinhole leaks as small as 10 µm (p < 0.05). Therefore, it can be concluded that the HVLD technique is a promising non‐destructive and on‐line method to detect pinhole defects, which may be applicable to a wide range of hermetically sealed packages. Copyright © 2013 John Wiley & Sons, Ltd.     

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter.     

Design of integrated 1×2, 1×4 low driving voltage polymer electro-optic switches based on Y-fed directional couplers

Two integrated 1 × 2 and 1 × 4 polymer electro-optic switches based on Y-fed directional couplers are designed and optimized in terms of the coupled mode theory, electro-optic modulation theory, conformal transforming method and image method. The principle of the 1 × 2 electro-optic switch is described. Parameters including the core size, buffer layer thickness, electrode thickness, electrode width and electrode gap are optimized. Simulation results show that the length of the designed 1 × 2 switch is about 3.126 mm, the driving voltages of the two branches are as low as 0.891 and ?0.891 V, respectively, the crosstalk and insertion loss are less than ?30 and 1.42 dB, respectively, within the operation wavelength from 1527 to 1574 nm. Under the same driving voltages, the 1 × 4 optical switch with a total length of less than 7 mm can be switched by altering the voltages applied on the electrodes of the three Y-fed directional couplers. Simulation results from the beam propagation method (BPM) indicate that the two designed devices exhibit favorable switching functions.     

Controlled deposition of new organic ultrathin film as a gate dielectric layer for advanced flexible capacitor devices

This letter describes a new organic (1-bromoadamantane) ultrathin film as gate dielectric, which was successfully deposited by sol–gel spin-coating process on a flexible polyimide substrate at room temperature. The metal–insulator-metal (MIM) device with organic (1-bromoadamantane) ultrathin (10 nm) film as gate dielectric layer operated at gate voltage of 5.0 V, showing a low leakage current density (5.63 × 10^?10 A cm^?2 at 5 V) and good capacitance (2.01 fF μm^?2 at 1 MHz). The chemical structure of the 1-bromoadamantane layer was investigated by Fourier transform infrared spectrometer. The excellent leakage current density and better capacitance, probably due to the presence of polar, non-polar, low-polar groups, and bromine atoms in ultrathin film. Practical properties of the film in MIM capacitor such as dielectric constant as well as bending result of leakage current density and breakdown voltage have been better related to such fundamental adhesion nature over flexible substrate. This permits estimation of the properties of new dielectric in thin film form and short lists of the best materials for low loss and good capacitance flexible capacitors could be drawn up in future.     

基于介质工程研制高性能黑磷顶栅器件

在这个工作中,作者通过电子束沉积二氧化铪(HfO₂)作为栅介质,并沉积1nm锡(Sn)作为生长HfO₂的缓冲层,获得了场效应迁移率超过100cm²V^-1s^-1的黑磷(BP)顶栅场效应晶体管(TG-FETs)。通过测试BP TG-FETs在不同漏源电压下的转移特性曲线,发现了漏极偏压会引起栅控效应。进一步地,在较小电压下探究了BP TG-FETs不同沟道长度的源漏电流饱和情况,这可用于BP射频器件的研究。最后,对BP顶栅器件的量子电容进行了相关研究,从测量的C-V曲线和转移特性曲线中直接提取并计算出栅介质氧化物电容和BP量子电容,此过程无需再引入任何其他拟合参数,BP量子电容的测量也为探索BP的态密度和电子器件可压缩性提供了重要依据。     

High‐Performance Flexible Organic Nano‐Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles

Nano‐floating gate memory (NFGM) devices are transistor‐type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe₂O₄) nanoparticles (NPs) as charge trap sites and pentacene as a p‐type semiconductor. Monodisperse CoFe₂O₄ NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle–particle interactions. CoFe₂O₄ NP‐based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I_on/I_off) of ≈2.98 × 10³_, and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe₂O₄ NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high‐performance organic memory devices.     

Growth and characterization of HfO2 high-k gate dielectric films by laser molecular beam epitaxy (LMBE)

The HfO₂ gate dielectric films were fabricated by the laser molecular beam epitaxy (LMBE) technique. High-resolution transmission electron microscopy (HRTEM) observation showed that under optimized condition, there is no detectable SiO₂ interfacial layer in the as-deposited film and a SiO₂ interfacial layer of about 0.4 nm was formed at the Si interface due to the post deposition annealing. Capacitance–voltage (C–V) measurement of the film revealed that the equivalent oxide thickness was about 1.3 nm. Such a film showed very low leakage current density of 1.5 × 10⁻² A cm⁻² at 1 V gate bias from the current–voltage (I–V) analysis. The conduction mechanisms as a function of temperature T and electric field E were also systematically studied.     

Multimode Hydraulically Amplified Electrostatic Actuators for Wearable Haptics

The sense of touch is underused in today’s virtual reality systems due to lack of wearable, soft, mm-scale transducers to generate dynamic mechanical stimulus on the skin. Extremely thin actuators combining both high force and large displacement are a long-standing challenge in soft actuators. Sub-mm thick flexible hydraulically amplified electrostatic actuators are reported here, capable of both out-of-plane and in-plane motion, providing normal and shear forces to the user’s fingertip, hand, or arm. Each actuator consists of a fluid-filled cavity whose shell is made of a metalized polyester boundary and a central elastomer region. When a voltage is applied to the annular electrodes, the fluid is rapidly forced into the stretchable region, forming a raised bump. A 6 mm × 6 mm × 0.8 mm actuator weighs 90 mg, and generates forces of over 300 mN, out-of-plane displacements of 500 µm (over 60% strain), and lateral motion of 760 µm. Response time is below 5 ms, for a specific power of 100 W kg⁻¹. In user tests, human subjects distinguished normal and different 2-axis shear forces with over 80% accuracy. A flexible 5 × 5 array is demonstrated, integrated in a haptic sleeve.     

Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric

A self-assembled film of gold nanoparticles is integrated into the gate dielectric of an organic thin-film transistor to produce memory effects. The transistor is fabricated on a heavily doped n-type silicon (n/sup +/-Si) substrate with a thermally grown oxide layer of 100 nm thick. n/sup +/-Si serves as the gate electrode while the oxide layer functions as the gate dielectric. Gold nanoparticles as the floating gate for charge storage are deposited on the gate oxide by electrostatic layer-by-layer self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Gold nanoparticles are charged or discharged with different gate bias so that the channel conductance is modulated. The memory transistor has an on/off ratio over 1500 and data retention time of about 200 s. The low-temperature solution-based process is especially suitable for plastic-based circuits. Therefore, the results of this study could accelerate achievement of cheap and flexible organic nonvolatile memories.     

Solution Combustion Synthesis: Low‐Temperature Processing for p‐Type Cu:NiO Thin Films for Transparent Electronics

Low‐temperature solution processing opens a new window for the fabrication of oxide semiconductors due to its simple, low cost, and large‐area uniformity. Herein, by using solution combustion synthesis (SCS), p‐type Cu‐doped NiO (Cu:NiO) thin films are fabricated at a temperature lower than 150 °C. The light doping of Cu substitutes the Ni site and disperses the valence band of the NiO matrix, leading to an enhanced p‐type conductivity. Their integration into thin‐film transistors (TFTs) demonstrates typical p‐type semiconducting behavior. The optimized Cu_5%NiO TFT exhibits outstanding electrical performance with a hole mobility of 1.5 cm² V^?1 s^?1, a large on/off current ratio of ≈10⁴, and clear switching characteristics under dynamic measurements. The employment of a high‐k ZrO₂ gate dielectric enables a low operating voltage (≤2 V) of the TFTs, which is critical for portable and battery‐driven devices. The construction of a light‐emitting‐diode driving circuit demonstrates the high current control capability of the resultant TFTs. The achievement of the low‐temperature‐processed Cu:NiO thin films via SCS not only provides a feasible approach for low‐cost flexible p‐type oxide electronics but also represents a significant step toward the development of complementary metal–oxide semiconductor circuits.     

Graphene–Graphene Oxide Floating Gate Transistor Memory

A novel transparent, flexible, graphene channel floating‐gate transistor memory (FGTM) device is fabricated using a graphene oxide (GO) charge trapping layer on a plastic substrate. The GO layer, which bears ammonium groups (NH₃⁺), is prepared at the interface between the crosslinked PVP (cPVP) tunneling dielectric and the Al₂O₃ blocking dielectric layers. Important design rules are proposed for a high‐performance graphene memory device: i) precise doping of the graphene channel, and ii) chemical functionalization of the GO charge trapping layer. How to control memory characteristics by graphene doping is systematically explained, and the optimal conditions for the best performance of the memory devices are found. Note that precise control over the doping of the graphene channel maximizes the conductance difference at a zero gate voltage, which reduces the device power consumption. The proposed optimization via graphene doping can be applied to any graphene channel transistor‐type memory device. Additionally, the positively charged GO (GO–NH₃⁺) interacts electrostatically with hydroxyl groups of both UV‐treated Al₂O₃ and PVP layers, which enhances the interfacial adhesion, and thus the mechanical stability of the device during bending. The resulting graphene–graphene oxide FGTMs exhibit excellent memory characteristics, including a large memory window (11.7 V), fast switching speed (1 μs), cyclic endurance (200 cycles), stable retention (10⁵ s), and good mechanical stability (1000 cycles).     

High-performance carbon nanotube field effect transistors with a thin gate dielectric based on a self-assembled monolayer

Individual single-walled carbon nanotube (SWCNT) field effect transistors (FETs) with a 2 nm thick silane-based organic self-assembled monolayer (SAM) gate dielectric have been manufactured. The FETs exhibit a unique combination of excellent device performance parameters. In particular, they operate with a gate-source voltage of only -1 V and exhibit good saturation, large transconductance, and small hysteresis (相似文献   

Solid‐State Electrolyte‐Gated Graphene in Optical Modulators

The gate‐tunable wide‐band absorption of graphene makes it suitable for light modulation from terahertz to visible light. The realization of graphene‐based modulators, however, faces challenges connected with graphene's low absorption and the high electric fields necessary to change graphene's optical conductivity. Here, a solid‐state supercapacitor effect with the high‐k dielectric hafnium oxide is demonstrated that allows modulation from the near‐infrared to shorter wavelengths close to the visible spectrum with remarkably low voltages (≈3 V). The electroabsorption modulators are based on a Fabry–Perot‐resonator geometry that allows modulation depths over 30% for free‐space beams.     

Flexible Organic/Inorganic Hybrid Near‐Infrared Photoplethysmogram Sensor for Cardiovascular Monitoring

Wearable photoplethysmogram (PPG) sensors offer convenient and informative measurements for evaluating daily physiological states of individuals. In this work, epidermal and flexible near‐infrared (NIR) PPG sensors integrating a low‐power, high‐sensitivity organic phototransistor (OPT) with a high‐efficiency inorganic light‐emitting diode are developed. By exploiting an organic bulk heterojunction active layer and a bilayer gate dielectric design, a low voltage (<3 V) operated OPT with NIR responsivity as high as 3.5 × 10⁵ A W^?1 and noise equivalent power of 1.2 × 10^?15 W Hz^?1/2 is achieved, greatly surpassing commercial available silicon‐based photodetectors. In addition, the ultrathin encapsulation structure renders the device highly flexible and allows transfer printing of the device directly onto human skin. It is demonstrated that the epidermal/flexible PPG sensors are capable of continuously monitoring heart rate variability and precisely tracking the changes of pulse pressure at different postures of human subjects with the aid of electrocardiogram monitoring, exhibiting more reliable performance than commercial PPG sensors while consuming less power. The study suggests that the hybrid PPG sensor design may provide a promising solution for low‐power, real‐time physiological monitoring.     

Synaptic Barristor Based on Phase‐Engineered 2D Heterostructures

The development of energy‐efficient artificial synapses capable of manifoldly tuning synaptic activities can provide a significant breakthrough toward novel neuromorphic computing technology. Here, a new class of artificial synaptic architecture, a three‐terminal device consisting of a vertically integrated monolithic tungsten oxide memristor, and a variable‐barrier tungsten selenide/graphene Schottky diode, termed as a ‘synaptic barrister,’ are reported. The device can implement essential synaptic characteristics, such as short‐term plasticity, long‐term plasticity, and paired‐pulse facilitation. Owing to the electrostatically controlled barrier height in the ultrathin van der Waals heterostructure, the device exhibits gate‐controlled memristive switching characteristics with tunable programming voltages of 0.2?0.5 V. Notably, by electrostatic tuning with a gate terminal, it can additionally regulate the degree and tuning rate of the synaptic weight independent of the programming impulses from source and drain terminals. Such gate tunability cannot be accomplished by previously reported synaptic devices such as memristors and synaptic transistors only mimicking the two‐neuronal‐based synapse. These capabilities eventually enable the accelerated consolidation and conversion of synaptic plasticity, functionally analogous to the synapse with an additional neuromodulator in biological neural networks.     

Stability of pentacene organic field effect transistors with a low-k polymer/high-k oxide two-layer gate dielectric

This paper reports on the processing and the characterization of pentacene organic field effect transistors (OFETs) with a two-layer gate dielectric consisting of a polymer (PMMA) on a high-k oxide (Ta₂O₅). This dielectric stack has been designed in view to combine low voltage operating devices, by the use of a high-k oxide which increases the charge in the accumulation channel and the gate capacitance, and highly stable devices which generally could be achieved with polymer dielectrics but not necessarily with strongly polar high-k oxides. Bi-layer dielectric devices were compared to those with only Ta₂O₅ or PMMA gate insulators. Bias stress at room temperature was used to assess the electrical stability. A very low operating voltage was achieved with Ta₂O₅ but these devices exhibit hysteresis and degraded characteristics upon bias stress. OFETs with PMMA revealed very stable but operate at rather a high voltage due to the low dielectric constant of PMMA. Reasonably stable devices operating at about 10 V could have been obtained with PMMA/Ta₂O₅ two-layer dielectric. The origin of observed threshold voltage shift and mobility decrease upon bias stress are discussed.