高速集成电路电源网络的频率特性分析

提出了用一种简单模型计算随频率变化的电感。由于稠密的部分电感矩阵使得方程求解非常困难，采用二次求逆的方法对其进行处理。采用频变电感的计算方法，分析了三种类型电源网络的电感随频率变化的特性。由计算结果可知，网络的回路电感随信号频率的升高呈下降趋势，且成对分布的电源网络的回路电感最小。这为电源网络的设计和同步开关噪声的分析提供了一定的依据。     

Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique

In this paper, an integrated adaptive-output switching converter is proposed. The design employs a one-cycle control for fast line regulation and a single outer loop for tight load regulation and fine tuning. A switched-capacitor integrator is introduced to the one-cycle control to obtain positive integration with a single positive power supply, allowing a standard low-cost CMOS fabrication process. To improve the efficiency, a dynamic loss control technique is presented. The converter was designed and fabricated with 0.35 $mu{hbox{m}}$ N-well CMOS process. With a supply voltage of 3 V, a voltage ripple of less than $pm$20 mV is measured. The maximum efficiency is 92% with a load power of 475 mW. The converter exhibits a tracking speed of 23.75 $mu{hbox{s/V}}$ for both start-up and reference voltage transitions. The recovery time for a 20% load change is approximately 9.5 $mu{hbox{s}}$.      

欧洲的供电电压

产品出口时,除了要符合进口国的安全标准要求以外,同时,也要注意产品外接供电电源接口的设计要符合进口国的供电制式,很多企业把设计用于国内使用的产品样品直接用于欧共体的CE认证或出口,导致试验不符合要求,更影响产品的销售。本文简要介绍欧洲的供电制式,以及在产品设计时如何能符合欧洲的供电制式。     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势．介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展．最后展望了集成电路芯片上光互连的应用前景．     

集成电路芯片上光互连研究的新进展

讨论了集成电路向高集成度、高工作频率和高传输速率继续发展时 ,常规金属互连出现的困难以及集成电路芯片上光互连具有的潜在优势 .介绍了组成芯片上光互连的光发射器件、光接收器件和光传输器件等三种基本器件及其与硅集成电路集成的研究新进展 .最后展望了集成电路芯片上光互连的应用前景 .     

Voltage Setup Problem for Embedded Systems With Multiple Voltages

We formulate the following voltage setup problem: how many levels and at which values should voltages be implemented on the system to achieve the maximum energy saving by dynamic voltage scaling (DVS)? This problem challenges whether DVS technique's full potential in energy saving can be reached on multiple voltage systems. In this paper, 1) we derive analytical solutions for dual-voltage system; 2) we develop efficient numerical methods for the general case where analytical solutions do not exist; 3) we demonstrate how to apply our proposed algorithms in system design; and 4) our experimental results suggest that, interestingly, multiple voltage systems with proper voltage setup can be very close to DVS technique's full potential in energy saving.     

On-Chip Liquid Cooling With Integrated Pump Technology

In this paper, the capability of a novel cooling system for microchannels based on the principle of electrowetting is examined. To start with, the elcctrowetting effect in microchannels is experimentally investigated. The used electrowetting system consists of a liquid droplet deposited on a conductive Si substrate and electrically insulated from this substrate by a dielectric, layer. Microchannels of 100 mum times 100 mum are etched in the substrate. By applying an ac voltage signal between the droplet and the substrate, the microchannels can be periodically tilled and emptied with the liquid of the droplet. This oscillating liquid flow will be used to cool the chip. For the 100 mum times 100 mum microchannels a voltage of 51 V is required for the actuation. Further, based upon the results of the filling of the channels the cooling capacity of the proposed system is theoretically investigated. The theoretically achievable cooling rate of this enhanced system is compared to the heat transfer by conduction through a silicon substrate. A critical filing period is found; for shorter filling periods, the heat transfer will be improved by inserting microchannels, for higher filling periods the electrowetting deteriorates the cooling. It can be concluded that the proposed system is promising, especially when frequencies in the range of a few Hz can be achieved.     

High-Performance On-Chip Transformers With Partial Polysilicon Patterned Ground Shields (PGS)

In this brief, we propose the concept of "partial patterned ground shields (PGSs)" to improve the performances of RF passive devices, such as inductors and transformers. Partial PGS can be achieved after the redundant PGS of a traditional complete PGS, which is right below the spiral metal lines of an RF passive device, is removed for the purpose of reducing the large parasitic capacitance. A set of test transformers has been implemented to demonstrate the partial PGS. The results show that when the partial PGS was adopted, a 56.5% (from 6.12 to 9.58) and a 55.7% (from 5.55 to 8.64) increase in Q-factor, an 18.2% (from 0.67 to 0.79) and a 21.4% (from 0.66 to 0.8) increase in maximum available power gain (G_Amax), and an 18.4% (from 0.69 to 0.82) and a 21.2% (from 0.69 to 0.83) increase in magnetic-coupling factor (k_im) were achieved at 4.2 and 5.2 GHz, respectively, for a bifilar transformer with an overall dimension of 230times215 mum². Furthermore, compared with the transformer with traditional PGS, a 9.9% (from 10.1 to 11.1 GHz) increase in resonant frequency (f_SR), a 38% (from 6.94 to 9.58) increase in Q-factor at 4.2 GHz, and a 5.3% (from 0.75 to 0.79) increase in G_Amax at 4.2 GHz were obtained. These results demonstrate that the proposed partial PGS is very promising for high-performance RF-ICs applications     

电源应用集成功率半导体器件

ISOPLUS 14IM系列功率半导体器件提供的性能使其非常适合开关模式电源(SMPS)应用:集成度高、工作特性可针对高开关频率优化、集成隔离/绝缘措施可以简化安装,此外对于高电压应用如果需要的话还可提供较大的防放电和漏电间隔。本文详细介绍了这些器件所使用的技术,并特别针对开关电源应用讨论了其特性。     

An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells

A stabilized power supply realized by chip-integrated micro fuel cells within an extended CMOS process is presented in this paper. The fuel cell system delivers a maximum power output of 450 ? W/cm². The electronic control circuitry consists of an LDO, an on-chip oscillator and a programmable timing network. The core system consumes an average power of 620 nW. The system reaches a current efficiency of up to 92% and provides a constant output voltage of 3.3 V.     

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.      

双极型功率集成电路版图设计技术

双极型功率集成电路已大量应用于民用、军用电子设备中,其典型应用主要是在通信系统、雷达和电子对抗等领域.大功率电子设备的性能与可靠性很大程度上取决于双极功率器件及其放大电路的性能,因此,提高双极型功率集成电路的性能和可靠性具有十分重要的现实意义.在分析双极功率器件和集成电路工作特点的基础上,介绍了器件结构及其版图设计方法,详细分析了其特点和功能,以达到提高双极型功率集成电路性能和可靠性的目的.     

电力电子集成电路的静电放电（ESD）保护

本文描述了ESD的基本概念，介绍了电力电子集成电路的ESD保护方法和技术。最后，指出了在版图设计中应注意的一些问题。     

Modified Wilkinson Power Dividers for Millimeter-Wave Integrated Circuits

A modification of the Wilkinson power divider is presented that eases planar implementation while maintaining performance. By adding transmission lines between the resistor and the quarter-wave transformers of the traditional design, a range of valid solutions exists that meet the conditions of being reciprocal, isolated between the output ports, and matched at all ports. The proposed design is particularly useful at millimeter-wave frequencies where reduced physical dimensions make a circuit configuration suitable for low-cost package-level implementation difficult using traditional methods. Two frequency bands are demonstrated. At V-band, the circuit gives 0.3-dB excess insertion loss, 19-dB isolation, and 50% bandwidth. At the W-band, the circuit gives 0.75-dB excess insertion loss, 24-dB isolation, and 39% bandwidth.     

新型功率混合集成电路材料—氮化铝（A1N）

本文主要介绍了A1N的成瓷工艺,金属化方法,特性及在新型电子器件中的应用示例,A1N在功率电子领域有限取代BeO,成为本世纪大量应用的主导电子材料。     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

基于DSP的高性能谐波功率电源

介绍一种以DSP为核心的便携谐波功率电源,论述了该电源的工作原理、技术要点及软件设计思想。针对电力部门对电网运行质量进行检测的要求,可以实现对有谐波含量的仪器、仪表计量误差校验。     

On-Chip Thermal Management With Microchannel Heat Sinks and Integrated Micropumps

Liquid-cooled microchannel heat sinks are regarded as being amongst the most effective solutions for handling high levels of heat dissipation in space-constrained electronics. However, obstacles to their successful incorporation into products have included their high pumping requirements and the limits on available space which precludes the use of conventional pumps. Moreover, the transport characteristics of microchannels can be different from macroscale channels because of different scaling of various forces affecting flow and heat transfer. The inherent potential of microchannel heat sinks, coupled with the gaps in understanding of relevant transport phenomena and difficulties in implementation, have guided significant research efforts towards the investigation of flow and heat transfer in microchannels and the development of microscale pumping technologies and novel diagnostics. In this paper, the potential and capabilities of microchannel heat sinks and micropumps are discussed. Their working principle, the state of the art, and unresolved issues are reviewed. Novel approaches for flow field measurement and for integrated micropumping are presented. Future developments necessary for wider incorporation of microchannel heat sinks and integrated micropumps in practical cooling solutions are outlined.     

Test Planning for Core-based Integrated Circuits under Power Constraints

This paper addresses reduction of test cost for core-based non-stacked integrated circuits (ICs) and stacked integrated circuits (SICs) by test planning, under power constraint. Test planning involves co-optimization of cost associated with test time and test hardware. Test architecture is considered compliant with IEEE 1149.1 standard. A cost model is presented for calculating the cost of any test plan for a given non-stacked IC and a SIC. An algorithm is proposed for minimizing the cost. Experiments are performed with several ITC’02 benchmark circuits to compare the efficiency of the proposed power constrained test planning algorithm against near optimal results obtained with Simulated Annealing. Results validate test cost obtained by the proposed algorithm are very close to those obtained with Simulated Annealing, at significantly lower computation time.     

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 $mu {hbox {m}} times,55 mu{hbox {m}}$, uses decoupling capacitance to sense noise and inject a proportional current into $V _{rm SS}$ as a method of reduction. A chip has been designed and fabricated using TSMC's 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.