片内光通信技术综述

在纳米工艺水平下,传统的铜线互连已经很难满足集成电路芯片在延迟、带宽、功耗等方面的要求,片内通信问题已经成为集成电路设计的瓶径.文中根据片内光器件集成技术的最新进展,介绍了采用片内光互连代替电互连的最新技术及其性能方面的优势.文中重点总结了片内光互连的三种典型应用.首先,介绍了片内光时钟分布网络;其次,从应用的角度分析了光电总线结构相对于单纯电总线在性能上的提升;最后,介绍了一种新的片上光网络,它集成了片内电的包交换控制网络和宽带电路交换光网络.仿真和实验结果表明,光互连能够为高集成度纳米级芯片提供高带宽、低延迟,小功耗的片内通信服务.     

Modellierungs- und Simulationsverfahren für die optische Verbindungstechnik auf elektrischen Leiterplatten

Optical interconnection technology on the printed circuit board level is a key technology for future microelectronic equipment. The consideration of functional, technological, and economical requirements results in a hybrid solution, where electrical and optical interconnects are integrated into one substrate called electrical optical printed circuit board. The significant part of the entire design process for electrical optical printed circuit boards is marked by the design supporting modelling and simulation of optical interconnects. Based on an abstract model for an entire optical interconnect a simulation model for optical multimode-waveguides is presented, taking into account all significant waveguide properties. Apart from that, the modeling of active components (laser- and photo-diodes) is addressed.     

On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects

Parallel repeaters are proven to outperform serial repeaters in terms of delay, power and silicon area when regenerating signals in system-on-chip (SoC) interconnects. In order to avoid fundamental weaknesses associated with previously published parallel repeater-insertion models, this paper presents a new mathematical modeling for parallel repeater-insertion methodologies in SoC interconnects. The proposed methodology is based on modeling the repeater pull-down resistance in parallel with the interconnect. Also, to account for the effect of interconnect inductance, two moments were used in the transfer function, as opposed to previous Elmore delay models which consider only one moment for RC interconnects. A direct consequence of this new type of modeling is an increased challenge in the mathematical modeling of interconnects. HSpice electrical and C++/MATLAB simulations are conducted to assess the performance of the proposed optimization methodology using a 0.25-$mu$m CMOS technology. Simulation results show that this repeater-insertion methodology can be used to optimize SoC interconnects in terms of propagation delay, and provide VLSI/SoC designers with optimal design parameters, such as the type as well as the position and size of repeaters to be used for interconnect regeneration, faster than with conventional HSpice simulations.      

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers

In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried out that takes interconnect parasitics into account, and analytical design criteria are then derived by assuming that the MUX switches are made up of pass transistors or transmission gates, as is often done in practical cases. The design criteria turn out to be very simple (even more than those in [1] which did not consider the effect of interconnects) and independent of the adopted technology. In addition, an approximate delay expression is given to predict the achievable speed performance before actually carrying out the optimized design. The results are validated through post-layout simulations on a 90-nm CMOS process.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

Polylithic Integration of Electrical and Optical Interconnect Technologies for Gigascale Fiber-to-the-Chip Communication

Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.     

Design and Fabrication of FlexConnects: A Cost-Effective Implementation of Compliant Chip-to-Substrate Interconnects

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such “compliant interconnects” are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. This paper presents two concepts to address this. First, an innovative, cost-effective fabrication process to realize compliant interconnects is proposed. Sequential lithography and electroplating processes with up to two masking steps are utilized. Such an approach potentially reduces the cost of fabricating compliant interconnects. Second, an innovative approach to designing compliant interconnects is proposed to improve electrical performance without compromising on mechanical reliability. The new approach uses parallel/multiple electrical paths as part of the compliant interconnect design. These concepts are integrated to realize a new compliant interconnect technology called FlexConnects. Utilizing the proposed fabrication process parallel-path FlexConnects are realized at a 100- $mu{hbox {m}}$ pitch. Numerical simulations are used to demonstrate that the electrical performance of parallel-path FlexConnects (self inductance of $sim$ 37 pH) is enhanced without compromising on mechanical performance, validating the use of parallel/multiple electrical paths in the interconnect design.      

Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect

Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper describes a systematic, fully automated synthesis method for integrated microsource-based optical interconnect capable of optimally sizing the interface circuits based on system specifications, CMOS technology data, and optical device characteristics. The simulation-based nature of the design method means that its results are relatively accurate, even though the generation of each data point requires only 5 min on a 1.3-GHz processor. This method has been used to extract typical performance metrics (delay, power, interconnect density) for optical interconnect of length 2.5-20 mm in three predictive technologies at 65-, 45-, and 32-nm gate length.     

Designing fast on-chip interconnects for deep submicrometer technologies

This paper proposes a solution to the problem of improving the speed of on-chip interconnects, or wire delay, for deep submicron technologies where coupling capacitance dominates the total line capacitance. Simultaneous redundant switching is proposed to reduce interconnect delays. It is shown to reduce delay more than 25% for a 10-mm long interconnect in a 0.12-/spl mu/m CMOS process compared to using shielding and increased spacing. The paper also proposes possible design approaches to reduce the delay in local interconnects.     

Monolithic integration of diffractive lenses with LED-arrays forboard-to-board free space optical interconnect

Since optical interconnections can severely reduce problems associated with electrical interconnect technology (including bandwidth limitations, electromagnetic cross talk, signal delay and EMI aspects), the development of suitable electrooptic components is of crucial importance for implementation of optical interconnects in future computer systems. This paper addresses the design, modeling, fabrication as well as experimental assessment of LED-arrays, with diffractive lenses etched into the rear side of the LED-substrate. The suitability of such optical sources for board-to-board optical interconnections will be demonstrated     

Device Requirements for Optical Interconnects to Silicon Chips

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.     

An approach to the optical interconnect made in standard CMOS process

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide,metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.     

Design and analysis of an optical waveguide tap for silicon CMOScircuits

A compact low-loss optical tap technology is critical for the incorporation of optical interconnects into mainstream complementary metal-oxide-semiconductor (CMOS) processes. For this work, an effort has been made to establish an optimal integrated optical tap design in terms of optical loss, bandwidth, economy, and process compatibility with multimetal layer CMOS circuits. A new device, which is based on a variation of the multimode interference effect, has been found to be especially promising. Two-dimensional (2-D) and three-dimensional (3-D) simulation results show low excess optical loss (<0.1 dB) for the design, and a nominal 40% (2.2 dB) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated tap devices are on the order of 15 [tin in length. Polymer waveguide materials are targeted for tap fabrication due to planarization properties, low cost, broad index control, and poling abilities for modulation-tuning functions. Low-cost silicon CMOS-based processing makes the new tap technology especially suitable for computer multichip module and board level interconnects, as well as for metro fiber to the home and desk telecommunications applications     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

An analysis of interconnect delay minimization by low-voltage repeater insertion

The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion.     

互连线和CMOS模型对性能影响的分析

在集成电路中,全局互连线的设计是关键.分析了互连线RC和RLC模型的不同特性;针对互连线与CMOS器件级联的电路进行分析.分析了集成电路中互连线和CMOS的模型对性能的影响,并给出了基于HSPICE软件的仿真结果.仿真结果表明,不同互连线和CMOS模型对系统传输特性有一定影响.     

Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-$muhbox{m}$ CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-$muhbox{m}$ -long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections.      

0.18 μm CMOS工艺下的互连线延迟和信号完整性分析

随着深亚微米工艺技术条件的应用和芯片工作频率的不断提高 ,芯片互连线越来越成为一个限制芯片性能提高和集成度提高的关键因素 :互连线延迟正逐渐超过器件延迟 ;互连线上信号传输时由于串扰引起的信号完整性问题已成为深亚微米集成电路设计所面临的一个关键问题。文中分析了芯片中器件和互连线的延迟趋势 ,模拟分析了 0 .1 8μm CMOS工艺条件下的信号完整性问题。     

一种基于Birnbaum-Saunders分布的新型互连时延统计模型

基于统计概率分布的互连时延模型具有效率高、准确性好的特点,但此类方法往往包含一些查表运算.本文提出了一种基于Birnbaum-Saunders分布的互连线时延模型,避免了查表运算,且仅需要采用前两个瞬态,计算简单,准确性较好,并提出了一种精度修正算法,使该方法具有更好的适应性.