共查询到20条相似文献,搜索用时 31 毫秒
1.
Hori A. Segawa M. Kameyama S. Yasuhira M. 《Electron Devices, IEEE Transactions on》1993,40(9):1675-1681
A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi2 film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 16 cm-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm 相似文献
2.
The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi 2 films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance 相似文献
3.
Mahapatra S. Rao V.R. Cheng B. Khare M. Parikh C.D. Woo J.C.S. Vasi J.M. 《Electron Devices, IEEE Transactions on》2001,48(4):679-684
Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si3N4 gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO2 gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si3N4 barrier (2.1 eV) is lower than the Si-SiO2 barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO2 MOSFETs 相似文献
4.
Miyamoto M. Toyota K. Seki K. Nagano T. 《Electron Devices, IEEE Transactions on》1999,46(8):1699-1704
A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration “pocket” layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-μm channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region 相似文献
5.
A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional ones. The electrical characteristics of this device are as good as those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3 V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily. 相似文献
6.
In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage. 相似文献
7.
《Solid-State Circuits, IEEE Journal of》1974,9(2):55-60
A knowledge of subthreshold behavior in an insulated gate field-effect transistor is important for circuits with low leakage specifications. This paper discusses the effect of drain voltage on the subthreshold region as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics. It is shown that all these effects can be incorporated into a simple one-dimensional model. 相似文献
8.
Ottomar Jäntsch 《Solid-state electronics》1982,25(1):59-61
A simple geometrical model allows the calculation of the threshold voltage of short and narrow channel MOSFETs as a function of gate length, gate width, source and drain depth, substrate voltage and source drain voltage. Input parameters of the program are the customary values such as oxide thickness and, furthermore, an effective impurity concentration in the field region. The flat band voltage and the effective impurity concentration in the channel region can be calculated by a modified SUPREM program. 相似文献
9.
Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm2/V-s, on/off current ratio larger than 108, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device 相似文献
10.
《Electron Devices, IEEE Transactions on》1987,34(1):19-27
A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n+-poly gate for n-channel and p+-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K. 相似文献
11.
Ching-Yuan Wu Shui-Yuan Yang Hsing-Hai Chen Fang-Churng Tseng Chih-Tay Shih 《Solid-state electronics》1984,27(7):651-658
Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation. 相似文献
12.
A novel electrically induced body dynamic threshold metal oxide semiconductor (EIB-DTMOS) is proposed where the body is electrically induced by substrate bias and its high performance is demonstrated by experiments and simulations. EIB-DTMOS achieves a large body effect and a low Vth at the same time. The upper limit of the supply voltage of the EIB-DTMOS is higher than that of a conventional DTMOS, because the forward biased p-n junction leakage current of the EIB-DTMOS is lower. Among several DTMOSs, the accumulation mode EIB-DTMOS shows the highest drive-current at fixed off-current due to a large Vth Shift (or large back gate capacitance) and a suppressed short channel effect 相似文献
13.
Jiang C. Tsui D.C. Lin B.J.F. Lee H. Lepore A. Levy M. 《Electron Device Letters, IEEE》1990,11(1):63-65
The subthreshold current of conventional GaAs/AlGaAs MODFETs and pseudomorphic InGaAs/AlGaAs MODFETs with the gate length down to 0.12 μm is investigated. The gate swing increases with the drain voltage and decreases with the gate length. It is attributed to charge injection from source to drain, limited by the channel potential barrier, which is a function of both the drain and the gate voltages. The pseudomorphic InGaAs/AlGaAs MODFETs show much better control than the conventional GaAs/AlGaAs MODFETs for the subthreshold current, especially with high drain biases. This shows that the pseudomorphic quantum-well structures can suppress the subthreshold current passing through the GaAs buffer region and reduce the undesirable short-channel effects 相似文献
14.
We describe a novel 2-dimensional metal-semiconductor field effect transistor (2-D MESFET) in which opposing Schottky side gates formed on the sidewall of a modulation-doped AlGaAs-InGaAs heterostructure modulate the channel width and the drain current. The drain current ranged from 0 to 210 μA and the maximum measured transconductance was 212 μS (212 mS/mm) at room temperature for a 1×1 micron channel. The threshold voltage was -0.45 V and the subthreshold ideality factor was 1.30. The estimated gate capacitance was 0.8 fF/μm, or about half the equivalent capacitance of conventional HFET's. The cutoff frequency fT was estimated to be 21 GHz. The narrow channel effect, which limits the minimum power consumption in conventional FET's, is practically eliminated in this device 相似文献
15.
Joachim H.-O. Yamaguchi Y. Ishikawa K. Inoue Y. Nishimura T. 《Electron Devices, IEEE Transactions on》1993,40(10):1812-1817
The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 μm. A doping effect is found which allows improvement of the S -factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S -factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S -factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found 相似文献
16.
A novel hetero-junction Tunnel-FET using Semiconducting silicide–Silicon contact and its scalability
Yan Wu Hiroyuki Hasegawa Kuniyuki Kakushima Kenji Ohmori Takanobu Watanabe Akira Nishiyama Nobuyuki Sugii Hitoshi Wakabayashi Kazuo Tsutsui Yoshinori Kataoka Kenji Natori Keisaku Yamada Hiroshi Iwai 《Microelectronics Reliability》2014
A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg2Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (Vd) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability. 相似文献
17.
The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiNx as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm2/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~106. Low off-state leakage current of 2.4×10-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved 相似文献
18.
Shiuh-Wuu Lee 《Electron Devices, IEEE Transactions on》1994,41(3):403-412
A capacitance based method for determining Lmet the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via two-dimensional numerical device simulation of MOSFETs with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting Lmet of MOSFETs with gate oxides thinner than 100 Å is better than 110 Å. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of Leff, the effective electrical channel length, from the drain current, Lmet is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFETs of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The Lmet and Leff extracted from measured capacitance and drain current data are compared. Results showed that L met is typically 700 to 1200 Å shorter for submicron MOS technologies, but it tracks with Leff, i.e. a shorter L met corresponds to a shorter Leff 相似文献
19.
Mohapatra N.R. Desai M.P. Narendra S.G. Rao V.R. 《Electron Devices, IEEE Transactions on》2002,49(5):826-831
The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (Kgate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum Kgate for different target subthreshold leakage currents has been identified 相似文献
20.
《Electron Device Letters, IEEE》1998,19(12):502-504
The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N2O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al2O3), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al2O3 gate dielectric layers. Typically, a field effect mobility of 47 cm2/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×105 at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al2 O3 and the SiGe channel layer is sufficiently passivated to make Al2O3 a better alternative to grown or deposited SiO2 for SiGe field effect devices 相似文献