CMOS四路可加权高频模拟开关的设计和研究

介绍了一种可对高频信号进行取样、加权、控制、叠加的模拟信号处理开关集成电路,通过两个高宽长比的高跨导NM O S晶体管可实现权值的粗调和微调。该电路采用标准0.6μm CM O S工艺制造。测试结果表明:该电路的工作频段为50~250 MH z时,导通时最小插入损耗约为-5.0~-10.5 dB,关断时隔离度可达-40.5~-23.4 dB左右;其连续可调的加权动态范围最大值为21.3 dB。     

CM7510系列CMOS高压模拟开关电路的研究

本文介绍CM7510系列CMOS高压模拟开关电路的设计,版图设计,工艺及电路性能。从理论和实验中分析了常规工艺中影响击穿电压的几个关键工艺参数。     

Analog VLSI Design Constraints of Programmable Cellular Neural Networks

Analog parallel signal processing systems, like cellular neural networks (CNN's), intrinsically have a high potential for perception-like signal processing tasks. The robust design of analog VLSI requires a good understanding of the capabilities as well as the limitations of analog signal processing. Implementation-oriented theoretical methods are described to compute the effect of all types circuit non-idealities with random or systematic causes on the static and dynamical behavior of CNN's and to derive specifications for the cell circuit building blocks. The fundamental impact of transistor mismatch on the trade-off between the speed, accuracy and power performance of CNN chips is demonstrated. A design methodology taking into account the effect of transistor mismatch is proposed and experimental results of a CNN chip implementation designed with this method are discussed.     

A High-Frequency Field-Programmable Analog Array (FPAA) Part 1: Design

The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.     

模拟集成电路设计工具的研究进展

介绍了模拟集成电路设计自动化工具的研究进展 ,详细叙述了有关模拟 IC设计自动化(DA)所用到的种种方法以及各种方法的优劣 ,提出了一些解决方案。介绍了模拟硬件描述语言(AHDLs)以及目前开发混合信号和混合层次 EDA的情况 ,最后叙述了所开发的基于知识的自动化器件产生器。器件产生器的设计思想有效地使用了电路模拟器和从它所得到的信息 ,且器件产生器自适应于工艺过程 ,因此既有基于模型设计系统的短设计时间 ,又有基于模拟设计系统的精确性 ,而且它提高了第一次投片成功率与设计周期之比。     

基于CMOS模拟电路的高速模糊神经网络设计

本文提出了可构成多规则模糊神经网络的CMOS模拟单元电路,包括:类Gauss型隶属度函数电路,电压求小电路和重心算法去模糊电路.基于这些电路设计了一个两输入/一输出、25条规则的控制系统,并通过非线性函数逼近进行了验证.所有单元均采用SMIC 0.18-μm CMOS数模混合工艺制造,芯片测试结果表明:提出的单元电路结构简单,输出电压偏差小,便于扩展和调节;因而适于实现多规则,自适应调节的高速高精度控制系统.     

一种低压高线性CMOS模拟乘法器设计

提出了一种新颖的CMOS四象限模拟乘法器电路．该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0．18μmCMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1．8V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0．3V,-3dB带宽可达到1GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。     

A Subthreshold PMOS Analog Cortex Decoder for the (8, 4, 4) Hamming Code

This paper presents a method for decoding high minimal distance (d_min) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d_min than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high d_min, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof‐of‐concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25‐μm CMOS. It outperforms an equivalent LDPC‐like decoder by 1 dB at BER=10^?5 and is 44 percent smaller and consumes 28 percent less energy per decoded bit.     

DPAD2—A Field Programmable Analog Array

DPAD2 is a Field Programmable Analog Array (FPAA) based on CMOS switched capacitor technology. This paper describes the major design decisions that went into creating DPAD2 with respect to the ultimate goal of the work, being a mixed signal field programmable silicon solution. Two major compromises exist in the design of an FPAA, one between flexibility and performance, the other between functionality and die size; DPAD2 overcomes the first with a novel field programmable hierarchic routing scheme and the second by careful analysis of many disparate designs to arrive at a best compromise solution. Results from prototype silicon are presented where a single analog cell is reconfigured to perform a number of different analog signal processing functions. Bandwidth of the DPAD2 device is 500 kHz and the SNR is typically 60 dB, although both are application dependent. Introduction of the FPAA now enables a designer to have working silicon within one day, by a simple configuration of the silicon chip via a PC parallel interface. Software libraries of analog circuits are provided and allow very rapid creation of large and complex analog circuits.     

非线性容差模拟电阻电路故障诊断神经网络方法

将线性电路故障定位 l1 范数最优化算法推广到非线性电路的故障定位 ,由于测后计算是基于神经网络计算机环境 ,所需时间较少 ,能满足现代工业实时性需要。实例和计算机模拟结果表明所提方法是可行的     

A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design

We present a voltage mode switched-capacitor Field Programmable Analog Array (FPAA) to be used to implement various analog circuits. The FPAA consists of uniform configurable analog blocks (CABs) allowing implementation of different functions. Each CAB consists of two back-to-back connected inverting and non-inverting strays-insensitive switched-capacitor integrators. The interconnection between CABs is implemented by switched and unswitched capacitor networks. The internal structure of CABs and the interconnection between different CABs are configured by user-programmable digital control signals. The functionality of the FPAA is demonstrated through embedding of different types of filters, programmable amplifiers, biquads, modulators and signal generators along with simulation results.     

工程硕士“模拟集成电路设计”课程探索

本文分析了集成电路专业工程硕士与普通硕士的异同.笔者针对工程硕士培养的教育目标和方向,结合近几年来的教学探索与实践,就工程硕士“模拟集成电路设计”课程在教学内容、教学方法和实验手段等方面进行了探讨,以适应培养复合型和实用性人才的需求.     

A System Design Methodology for Analog Feed Forward Artificial Neural Networks

Today Feed Forward Neural Networks (FFNs) use paradigms tied to mathematical frameworks more than to actual electronic devices. This fact makes analog neural integrated circuits heavy to design. Here we propose an alternative model that can use the native computational properties of the basic electronic circuits. A practical framework is described to train analog FFNs in compliance with the model. This is especially useful whenever the weight storage elements cannot be re-programmed on the fly at a high rate. To show how the capability of such framework can be applied to neural systems with non conventional architectures two cases are presented. The first one is a neural signal processor named NESP which has sigmoidal neurons and the other is an innovative architecture named N-LESS.     

变论域自适应模糊控制器的CMOS模拟电路芯片实现

为解决传统的自适应模糊控制器算法过于复杂难以用模拟电路实现的问题,本文研究了输入输出论域可随输入变量的变化而自适应变化的在线自适应模糊控制器及其在非线性系统控制中的应用,并制作了CMOS模拟电路芯片.提出了一种新的尖三角形隶属度函数实现输入变论域的功能,输出变论域部分采用对输入变量进行加权积分并求其绝对值的方法.控制器的其他部分为求小电路和重心法去模糊电路.以上各电路均为CMOS模拟电路,它们和集成的整体电路均在无锡上华(CSMC) 0.6μm工艺下流片,测试结果表明该芯片完成了变论域模糊控制器的功能.     

一种实用模拟温度控制电路设计

介绍了一种实用的模拟温度控制电路设计。该电路主要由运算放大器、单结晶体管及可控硅器件组成,通过比例积分、电压比较及移相触发等电路实现对电源输出功率大小进行控制,从而达到控制加热装置功率的目的。该电路温控精度较高、工作状态稳定可靠、实用性较强,可应用于工业温度控制场所。     

A Strategy for Rapid Mismatch Evaluation of Transient Characteristics of CMOS Analog Cells

A strategy is presented to evaluate the statistical means and standard deviations of the transient characteristics of CMOS analog cells. Based upon the Monte Carlo analysis of electrical simulations, this strategy follows a circuit-theory based approach achieving an important reduction on matrix ranges and consequently on the number of operations involved in the resolution of the circuit. The CPU time-consuming reduction is achieved also by saving information corresponding to the nominal transient analysis. We include comparative results for several CMOS cells showing the advantages of the proposed strategy.     

一种新的基于神经网络的模拟电路故障诊断系统

介绍了基于BP神经网络(BPNN)进行模拟电路故障诊断定位的理论,设计并实现以数字信号处理器(DSP)为核心的故障诊断系统.该系统采用模块化设计,具有扩充方便、高速采样的特点;将采样数据构成故障特征向量,利用BP网络训练这些特征向量并进行故障模式分类,实现模拟电路及PCB故障诊断.并给出了PCB板的故障诊断硬件结构及对单软和双软故障的诊断设计方法.     

一种低压BiCMOS四象限模拟乘法器的设计

提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。     

低压CMOS模拟与数字混合ASIC—瓦斯报警电路设计与制造

本文介绍一种单电源电压小于3V的低压CMOS模拟与数字混合ASIC——瓦斯报警电路的设计,并给出制造工艺的主要数据。本电路根据我厂的现有设备和工艺,采用正向设计,一次流片即获成功,批量生产重复性好。模拟线路的技术指标和数字线路的功能均达到预期的使用要求,3V工作时的驱动电流可达15mA。