Application of the low dielectric methyl-silsesquiazane (MSZ) as a passivation layer on TFT-LCD

In this study a low-k material, methyl-silsesquiazane (MSZ) has been investigated as a passivation dielectric layer for thin-film transistor (TFT) arrays. Compared with the conventional nitride film (k ∼ 7), the MSZ passivation layer exhibits a low residual stress and low dielectric constant (k ∼ 2.6) which lowers the RC delay in a device. The high transmittance and good planarization characteristics of a low-k MSZ film enhance the brightness and aperture ratio of thin-film transistors liquid crystal displays (TFT-LCDs).     

Substrate temperature effect on the SiC passivation layer synthesized by an RF magnetron sputtering method

This paper describes amorphous silicon carbide (a-SiC) film as an alternative material to silicon nitride (SiN) and silicon oxide (SiO₂) for the passivation layer of solar cells. We deposited the film on p-type silicon (100) wafers and glass substrates by RF magnetron sputtering using a SiC (99%) target. Structural and optical properties of the films were investigated according to the process temperature (room temperature, 300 °C, 400 °C, 500 °C and 600 °C). The structural properties were analyzed by Raman microscopy and XPS (X-ray Photoelectron Spectroscopy). The XPS showed that the content of SiC in the film is increased when the substrate temperature is higher. The optical properties of the films were examined by UV-visible spectroscopy and Ellipsometer. The optical characteristic measurement showed that the lowest refractive index of the film is 2.65. Also, using carrier lifetime measurement, we investigated the performance of SiC as the passivation layer. At the substrate temperature of 600 °C, we obtained a highest carrier lifetime of 7.5 μs.     

Paraffin wax passivation layer improvements in electrical characteristics of bottom gate amorphous indium–gallium–zinc oxide thin-film transistors

In this research, paraffin wax is employed as the passivation layer of the bottom gate amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs), and it is formed by sol–gel process in the atmosphere. The high yield and low cost passivation layer of sol–gel process technology has attracted much attention for current flat-panel-display manufacturing. Comparing with passivation-free a-IGZO TFTs, passivated devices exhibit a superior stability against positive gate bias stress in different ambient gas, demonstrating that paraffin wax shows gas-resisting characteristics for a-IGZO TFTs application. Furthermore, light-induced stretch-out phenomenon for paraffin wax passivated device is suppressed. This superior stability of the passivated device was attributed to the reduced total density of states (DOS) including the interfacial and semiconductor bulk trap densities.     

Amorphous oxide channel TFTs

Thin film transistors (TFTs) using amorphous oxides of post-transition metals: indium, gallium, and zinc for the channel materials are fabricated with radio-frequency magnetron sputtering methods for the deposition of the channel and the gate insulator layers, at room temperature with no high-temperature post-deposition annealing process. The TFTs operate as n-channel field-effect transistors with various structures of top/bottom gate and top/bottom source-and-drain contact including the inverse-stagger types, and with various materials for the gate insulators, the electrodes, and the substrates. The TFTs having smoother channel interfaces show the better performance at the saturation mobility beyond 10 cm² V^− 1 s^− 1 and the on-to-off current ratio over 10⁸ than the rough channel interfaces. The ring oscillator circuits operate with five-stage inverters of the top-gate TFTs or the inverse-stagger TFTs. Organic light-emission diode cells are driven by a simple circuit of the TFTs. It is also found by a combinatorial approach to the material exploration that the TFT characteristics can be controlled by the composition ratio of the metals in the channel layers. The amorphous oxide channel TFTs fabricated with sputtering deposition at low temperature could be a candidate for key devices of large-area flexible electronics.     

Organic FETs with HWCVD silicon nitride as a passivation layer and gate dielectric

This paper reports the use of hot-wire chemical vapour deposited (HWCVD) Silicon nitride as a passivation layer for Organic Field Effect Transistors (OFETs). Firstly, the degradation study of the OFETs is done with time. A thin (10-20 nm) layer of silicon nitride is deposited on the OFETs, at a low temperature (< 90 °C) by HWCVD process, to passivate them from the ambient. Our results show that this technique is very effective in improving the stability of the organic semiconductors (Poly-3-hexyl thiophene (P3HT) is used as a test case in this study). This HWCVD deposited nitride can also be used as a gate dielectric material for the study of OFETs because of its higher dielectric constant and significantly less hydrogen content.     

Negative bias–temperature stress in non-self-aligned p-channel polysilicon TFTs

The electrical instabilities in p-channel polysilicon TFTs induced by negative bias temperature stress (NBTS) and self-heating have been investigated. From NBTS experiments performed at different temperatures and gate bias, we derived an empirical relationship that provides the T and electric field dependence of the interface state generation. To explain the device instability related to self-heating we considered a spatially non uniform interface state distribution, as a non uniform transverse electric field is present during bias stress. The interface state distribution can be deduced using the empirical relationship, determined from NBTS experiments, and considering the spatial distribution of the oxide electric field, obtained from numerical simulations. Using the so determined interface state distribution it was possible to perfectly reproduce not only the transfer characteristics but also the asymmetry observed in the output characteristics, when source/drain contacts are reverted after bias stress.     

Laser ablated ZnO layers for ALGaN/GaN HEMT passivation

ZnO layer in a role of passivation of the AlGaN/GaN-based high electron mobility transistors (HEMTs) is presented. The thin layer is deposited by pulsed laser deposition technique. It is fully compatible with the process technology of high electron mobility transistors prepared on AlGaN/GaN heterostructures due to its physical properties similar to the GaN. We have succeeded to (1) suppress the gate leakage current; (2) increase the maximum of the drain current and the electron drift mobility, and (3) ensure the threshold voltage to be unaltered by employment of the thin ZnO layer to the channel area of the HEMT.     

ZnO thin films prepared by atomic layer deposition and rf sputtering as an active layer for thin film transistor

Recently, the application of ZnO thin films as an active channel layer of transparent thin film transistor (TFT) has become of great interest. In this study, we deposited ZnO thin films by atomic layer deposition (ALD) from diethyl Zn (DEZ) as a metal precursor and water as a reactant at growth temperatures between 100 and 250 °C. At typical growth conditions, pure ZnO thin films were obtained without any detectable carbon contamination. For comparison of key film properties including microstructure and chemical and electrical properties, ZnO films were also prepared by rf sputtering at room temperature. The microstructure analyses by X-ray diffraction have shown that both of the ALD and sputtered ZnO thin films have (002) preferred orientation. At low growth temperature T_s ≤ 125 °C, ALD ZnO films have high resistivity (> 10 Ω cm) with small mobility (< 3 cm²/V s), while the ones prepared at higher temperature have lower resistivity (< 0.02 Ω cm) with higher mobility (> 15 cm²/V s). Meanwhile, sputtered ZnO films have much higher resistivity than ALD ZnO at most of the growth conditions studied. Based upon the experimental results, the electrical properties of ZnO thin films depending on the growth conditions for application as an active channel layer of TFT were discussed focusing on the comparisons between ALD and sputtering.     

Evaluation of thin film passivation using inorganic Mg-Zn-F heterointerface for polymer light emitting diode

In this study, we manufactured Mg-Zn-F targets using magnesium fluoride (MgF₂) and zinc (Zn). The passivation films were deposited on a poly-ethylenenaphthalate (PEN) substrate using a radio-frequency magnetron sputter. The thickness of the manufactured passivation film was 120 nm. Among the three targets tested, the 4:6 weight target of MgF₂ to Zn resulted in films with the highest Zn content that would increase the packing density of the thin film. The water vapor transmission rate of a 120 nm Mg-Zn-F film prepared from this target and inserted between two 40 nm MgF₂ interlayers on PEN was 2.9 × 10^− 2 g/(m² day) at a relative humidity of 90% and a temperature 38 °C. Its optical transmittance was approximately 80%.     

Double layer SiNx:H films for passivation and anti-reflection coating of c-Si solar cells

In this report, we present a cost effective simple innovative approach to fabricate double layer anti-reflection (DLAR) coatings using a single material which can provide high qualities of passivation and anti-reflection property. Two layers of SiN_x:H films with different refractive indices were deposited onto p-type c-Si wafer using plasma enhanced chemical vapor deposition reactor by controlling the NH₃ and SiH₄ gas ratio. Refractive indices of top and bottom layers were chosen as 1.9 and 2.3 respectively. The effect of passivation at the interface was investigated by effective carrier lifetime, hydrogen concentration and interface trapped density (D_it) measurements. The optical characteristic was analyzed by reflectance and transmittance measurements. A superior efficiency of 17.61% was obtained for solar cells fabricated with DLAR coating when compared to an efficiency of 17.24% for cells with SLAR coating. Further, J_sc and V_oc of solar cell with DLAR coating is increased by a value of ~ 1 mA/cm² and 4 mV respectively than cell with SLAR coating.     

Experimental and modeling study of the capacitance-voltage characteristics of metal-insulator-semiconductor capacitor based on pentacene/parylene

The capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (MIS) capacitors consisting of pentacene as an organic semiconductor and parylene as the dielectric have been investigated by experimental, analytical, and numerical analysis. The device simulation was performed using two-dimensional drift-diffusion methods taking into account the Poole-Frenkel field-dependent mobility. Pentacene bulk defect states and fixed charge density at the semiconductor/insulator interface were incorporated into the simulation. The analysis examined pentacene/parylene interface characteristics for various parylene thicknesses. For each thickness, the corresponding flat band voltage extracted from the C-V plot of the MIS structure was more negative than − 2.4 V. From the flat band voltage the existence of a significant mismatch between the work functions of the gate electrode and pentacene active material has been identified. Experimental and simulation results suggest the existence of interface charge density on the order of 3 × 10¹¹ q/cm² at the insulator/semiconductor interface. The frequency dispersion characteristics of the device are also presented and discussed.     

Effect of reactive sputtered SiOx passivation layer on the stability of InGaZnO thin film transistors

We fabricated the indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with reactive sputtered SiO_x as passivation layer, and investigated the role of the SiO_x passivation layer in the IGZO-TFT under gate bias stress. The bias stability of IGZO-TFT with passivation layer is much better than that of IGZO-TFT without passivation layer. After applying positive bias stress of 20 V for 10000s, the device without passivation layer shows a larger positive V_th shift of 7.3 V. However, the device with passivation layer exhibits a much smaller V_th shift of 1.3 V. It suggests that V_th instability is attributed to the interaction between the exposed IGZO back surface and oxygen in ambient atmosphere during the positive gate voltage stress. The results indicate that reactive sputtered SiO_x passivation layer can effectively improve the bias stability of IGZO-TFT.     

Passivation layer effect on surface integrity induced by Cu-CMP

To achieve efficient Cu-Chemical-Mechanical Polishing planarization at miniaturized device dimensions, there is a need for a better understanding of the surface integrity induced by the process. Surface quality and stresses are the two selected indices in this article to evaluate the Cu-CMP process induced surface integrity. The thickness of the passivation layer and the penetration depth of abrasives are considered as the main effects for the generations of surface qualities and residual stress. Experimental validation on copper films on silicon wafer was performed by CMP with different pads and slurries to generate varied residual stresses and surface qualities. Depth of scratches and surface roughness were measured by the atomic force microscope. The stress measurements of the thin films were performed by a Grazing Incident X-ray diffraction instrument with its principles based upon modified sin²Ψ method. Accordingly, the surface roughness and stress were related to the thickness of the passivation layer and the CMP process conditions. When the penetration depth is larger than the passivation layer thickness, the roughness values are mainly decided by the selection of pads and the resultant penetration depth. In addition, the residual stress profiles are dependent on the CMP process conditions which include the slurries and pad parameters. The stress profile obtained for the slurry SDK with soft pad Politex composed smallest maximum tensile stress below the surface and a steady transition of stress profile compared to the stress profile obtained at the initial condition. At the condition for the same slurry SDK, but with a hard pad of IC1000, the CMP process induced larger maximum stress and sharper profile transition.     

Effect of magnesium oxide passivation on the performance of amorphous indium-gallium-zinc-oxide thin film transistors

Effect of hygroscopic magnesium oxide (MgO) passivation layer on the stability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) under positive bias stress and positive bias temperature stress has been investigated. The effect of MgO passivation has been observed by comparing the shift of the positive threshold voltage (V_th) after constant bias temperature stress, which were 8.2 V for the unpassivated TFTs and 1.88 V for the passivated TFTs.In addition, MgO passivated a-IGZO TFTs show also excellent stability under a humidity test since MgO passivation layer can prevent the penetration of water into back channel. In order to investigate the origin of humidity test result, we have measured X-ray photoelectron spectroscopy depth profile of both unpassivated and MgO passivated TFTs with a-IGZO back channel layers after N₂ wet annealing.