Reliability and performance scaling of very high speed SiGe HBTs

We discuss the SiGe HBT structural changes required for very high performance. The increase in collector concentration, affecting current density and avalanche current, appears to be the most fundamental concern for reliability. In device design, a narrow emitter and reduced poly–single-crystal interfacial oxide are important elements in minimizing device parameter shifts. From the application point of view, avalanche hot-carriers appear to present new constraints, which may be managed through limiting voltage (to 1.5×–2× BV_CEO), or through circuit designs robust to base current parameter shifts.     

Impact of geometrical scaling on low-frequency noise in SiGe HBTs

The influence of geometrical scaling on low-frequency noise in SiGe HBTs is presented. Small-size transistors show a strong variation in noise across many samples, whereas the noise in larger devices is more statistically reproducible. This size-dependent variation in noise can produce challenges for accurate compact modeling. This effect is investigated using reverse-bias emitter-base stress and calculations based on the superposition of generation/recombination noise.     

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 /spl mu//spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f/sub T//f/sub MAX/ values of 41/42 GHz were demonstrated for 0.5/spl times/10/spl mu/m/sup 2/ transistors.     

The effects of geometrical scaling on the frequency response andnoise performance of SiGe HBTs

We examine the geometrical scaling issues in SiGe HBT technology. Width Scaling, length scaling, and stripe-number scaling are quantified from a radio frequency (RF) design perspective at 2 GHz. We conclude that a SiGe HBT with emitter area A_E=0.5×20×6 μm² is optimum for low noise applications at J_c=0.1 mA/μm² and f=2 GHz using the design methodology, which guarantees optimal noise and input impedance matching with the simplest matching network. Finally, the optimal device sizes at f=4 and 6 GHz for low noise applications are also obtained using the same method     

Physical scaling rules for AlGaAs/GaAs power HBTs based on asmall-signal equivalent circuit

Physical scaling rules for AlGaAs/GaAs heterojunction bipolar transistors (HBTs) containing 2-16 emitter fingers are demonstrated, the parameter extraction is based on a small signal equivalent circuit. The scaling parameters compare favorably with the measured data from the process control monitor     

Half-terahertz operation of SiGe HBTs

This letter presents the first demonstration of a silicon-germanium heterojunction bipolar transistor (SiGe HBT) capable of operation above the one-half terahertz (500 GHz) frequency. An extracted peak unity gain cutoff frequency (f/sub T/) of 510 GHz at 4.5 K was measured for a 0.12/spl times/1.0 /spl mu/m/sup 2/ SiGe HBT (352 GHz at 300 K) at a breakdown voltage BV/sub CEO/ of 1.36 V (1.47 V at 300 K), yielding an f/sub T//spl times/BV/sub CEO/ product of 693.6 GHz-V at 4.5 K (517.4 GHz-V at 300 K).     

异质结晶体管的设计与性能

本文较详细地讨论了异质结晶体管的设计原理、材料选用和结构设计。在能带设计方面对宽发射区、缓变基区和多种收集区分别进行了讨论,比较了不同能带结构的优缺点。文章以晶体管的特征频率f_T和最高振荡频率f_(max)为例分析和比较了Ge/GaAs,Si/α-Si,GaAs/GaAlAs,InGaAsP/InP四种异质结晶体管的频率特性潜力。文章最后对目前常用的台面结构、平面结构、倒置结构作了介绍,并分析了它们的优缺点,简介了异质结的发展现状和发展方向。     

Mechanically strained Si-SiGe HBTs

The current gain (/spl beta/=I/sub C//I/sub B/) variations of the mechanically strained Si-SiGe heterojunction bipolar transistor (HBT) and Si bipolar junction transistor (BJT) devices are investigated experimentally and theoretically. The /spl beta/ change of HBT is found to be 4.2% and -7.8 under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. For comparison, there are 4.9% and -5.0 /spl beta/ variations for BJT under the biaxial compressive and tensile mechanical strain of 0.028%, respectively. In HBT, the mechanical stress is competing with the compressive strain of SiGe base, inherited from the lattice misfit between SiGe and Si. The current change due to externally mechanical stress is the combinational effects of the dependence of the mobility and the intrinsic carrier concentration on strain.     

亚微米自对准工艺

介绍了一种新的亚微米发射极窗口刻蚀工艺。利用ＲＩＥ技术和边墙隔离技术,无须对位光刻,使发射极窗口精确地位于发射区中央。该工艺简单,具有良好的可操作性和重复性。     

Submicron patterning of surfaces

A new process for providing submicron patterning of surfaces is presented. This processing technique, which the authors call the Iso-E process, is capable of producing submicron openings to the surface of materials using conventional photolithographic techniques and processing common to the semiconductor industry. This process can be used equally well with X-ray or electron-beam lithography to provide minimum geometry openings at minimum geometry spacings.     

Nonequilibrium electron transport in HBTs

Nonequilibrium electron transport in heterojunction bipolar transistors (HBTs) becomes clearly observable as their vertical dimensions are reduced, This is the reason for the superior tradeoff relationships between the device parameters and the resultant high-speed performance of HBTs fabricated with III-V semiconductor materials. This paper reviews the hot carrier effect in the base and the velocity overshoot effect in the collector and discusses the roles these effects play in reducing carrier traveling times and improving device performance     

RF linearity characteristics of SiGe HBTs

Two-tone intermodulation in ultrahigh vacuum/chemical vapor deposition SiGe heterojunction bipolar transistors (HBTs) were analyzed using a Volterra-series-based approach that completely distinguishes individual nonlinearities. Avalanche multiplication and collector-base (CB) capacitance were shown to be the dominant nonlinearities in a single-stage common emitter amplifier. At a given I_c an optimum V_ce exists for a maximum third-order intercept point (IIP3). The IIP3 is limited by the avalanche multiplication nonlinearity at low I_c, and limited by the C_CB nonlinearity at high I_c. The decrease of the avalanche multiplication rate at high I_c is beneficial to linearity in SiGe HBTs. The IIP3 is sensitive to the biasing condition because of strong dependence of the avalanche multiplication current and CB capacitance on I_c and V_ce. The load dependence of linearity was attributed to the feedback through the CB capacitance and the avalanche multiplication in the CB junction. Implications on the optimization of the transistor biasing condition and transistor structure for improved linearity are also discussed     

微波低噪声SiGe HBT的研制

利用3μm工艺条件制得SiGeHBT(HeterojunctionBipolarTransistor),器件的特征频率达到8GHz.600MHz工作频率下的最小噪声系数为1.04dB,相关功率增益为12.6dB,1GHz工作频率下的最小噪声系数为1.9dB,相关功率增益为9dB,器件在微波无线通信领域具有很大的应用前景     

微波低噪声SiGe HBT的研制

利用3μm工艺条件制得SiGe HBT(Heterojunction Bipolar Transistor),器件的特征频率达到8GHz.600MHz工作频率下的最小噪声系数为1.04dB,相关功率增益为12.6dB,1GHz工作频率下的最小噪声系数为1.9dB,相关功率增益为9dB,器件在微波无线通信领域具有很大的应用前景.     

Self-heating in multi-emitter SiGe HBTs

High power bipolar transistors often have multiple emitters, to achieve high currents, and efficient use of the whole emitter area. The emitters experience high current densities and are self-heated above the ambient temperature, leading to concerns about thermal run-away and damage to the device. Here we use a multi-emitter SiGe HBT, with multiple emitter contacts, to examine the temperature distribution in the emitters in such devices. We have measured the temperature increase in different emitters by biasing one emitter at a time and using the other base–emitter junctions as thermometers. We show that use of a selectively implanted collector does not alter the temperature increase or thermal coupling between the emitters.     

Growth of InGaN HBTs by MOCVD

The design and growth of GaN/InGaN heterojunction bipolar transistors (HBTs) by metalorganic chemical vapor deposition (MOCVD) are studied. Atomic-force microscopy (AFM) images of p⁺InGaN base layers (∼100 nm) deposited under various growth conditions indicate that the optimal growth temperature is limited to the range between 810 and 830°C due to a trade-off between surface roughness and indium incorporation. At these temperatures, the growth pressure must be kept above 300 Torr in order to keep surface pit density under control. An InGaN graded-composition emitter is adopted in order to reduce the number of V-shaped defects, which appear at the interface between GaN emitter and InGaN base and render an abrupt emitter-base heterojunction nearly impossible. However, the device performance is severely limited by the high p-type base contact resistance due to surface etching damage, which resulted from the emitter mesa etch.     

Modeling and analysis of ZnSe-Ge HBTs

A Gummel-Poon model is developed for ZnSe-Ge-GaAs heterojunction bipolar transistors (HBTs). In this structure, undoped Ge spacers are placed at the emitter-base and collector-base junctions. Injected current components as well as bulk, spacer, and space charge recombination current components are modeled. Early voltage and bandgap narrowing effects are included in the model. The device performance was simulated and compared with the experimental results. The paper shows a good agreement between our model and the experimental results. The paper shows also that using spacers would improve the device performance. The advantages of this model is that it is analytical, compact, and can be easily implemented in CAD tool programs to simulate single or double HBTs with similar or dissimilar materials structure for the emitter and collector.     

Proposal and demonstration of multi-emitter HBTs

The authors have designed and tested InGaAs-InAlGaAs multi-emitter HBTs (ME-HBTs). The emitter electrodes of the transistor work as both an emitter and a base depending on their potential. A highly doped emitter layer was used for a low turn-on voltage for the collector current. Using an ME-HBT, the room-temperature operation of AND/NOR gates was tested     

深亚微米光刻技术

超大规模集成电路（ＶＬＳＩ）线宽的不断缩小,促进了光刻技术的发展和分辨率的提高,使分辨率已进入到深亚微米区域。光学光刻分辨率的提高是依靠缩短曝光波长、增大透镜系统的数值孔径（ＮＡ）、采用新技术改进掩模和光学系统的设计以及提高光致抗蚀剂的性能来实现的。在简要的介绍了ＶＬＳＩ发展趋势的基础上,论述了深紫外光刻（ＤＵＶＬ）、极紫外光刻（ＥＵＶＬ）和Ｘ射线光刻技术取得的重要成果及面临的问题和可能解决的途径。