基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

基于CSD算法的高阶FIR滤波器优化设计

在通信或雷达领域的高速实时信号处理中,通常包含大量的高速高阶FIR滤波器的设计。例如在雷达信号处理中,要进行数字正交采样和脉冲压缩器的设计,要求滤波器速率高,阶数大,运算量非常大。若使用DSP芯片则需多片处理完成,使得系统的工作延迟长、成本高、功耗大、调试困难。该文根据CSD（Canonic Signed—Digital）算法的思想,实现了高阶高速FIR滤波器的优化设计。该算法可显著降低算法的运算量,可用可编程逻辑器件迅速快捷地完成系统的硬件设计。文中举例用Altera公司的FPGA来实现数字正交采样和脉冲压缩滤波器算法优化,进行了实验验证,最后给出了结果比较和分析,证明这对基于FPGA的高阶FIR滤波器的设计有实际意义。     

FIR filters with field-programmable gate arrays

Distributed arithmetic techniques are the key to efficient implementation of DSP algorithms in FPGAs. The distributed arithmetic process is briefly described. A representative DSP design application in the form of an 8 tap FIR filter is offered for the Xilinx XC3042 field programmable logic array (FPGA). The design is presented in sufficient detail—from filter specifications via filter design software through detailed logic of salient data and control functions to obtain a realistic placing and routing of configurable logic block (CLBs) and in/out block (IOBs) components for simulation verification and performance evaluation vis-a-vis commercially available dedicated 8 tap FIR filter chips.     

基于分布式算法的高阶FIR滤波器及其FPGA实现

随着FPGA技术的稳步提高,FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题,提出了一种采用基于位级联的多查找表分布式算法,并以一个32阶8位低通FIR滤波器为例,验证了所提出的方法。仿真结果表明,采用这种方法大大减少了FPGA硬件资源的耗费。     

基于FPGA的FIR滤波器高效实现

本文针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行研究,首先给出了将乘法转化为查表的DA算法,然后简要介绍整数的CSD表示和我们根据FPGA实现要求改进的最优表示;接着,本文讨论了在离散系数空间得到FIR滤波器系数最优解的混合整数规划方法;最后采用这一方法设计了最优表示离散系数FIR滤波器,通过FPGA仿真验证这一方法是可行的和高效的.     

Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic

Field-programmable logic (FPL), often grouped under the popular name field-programmable gate arrays (FPGA), are on the verge of revolutionizing sectors of digital signal processing (DSP) industry as programmable DSP microprocessor did nearly two decades ago. Historically, FPGAs were considered to be only a rapid prototyping and low-volume production technology. FPGAs are now attempting to move into the mainstream DSP as their density and performance envelope steadily improve. While evidence now supports the claim that FPGAs can accelerate selected low-end DSP applications (e.g., FIR filter), the technology remains limited in its ability to realize high-end DSP solutions. This is due primarily to systemic weaknesses in FPGA-facilitated arithmetic processing. It will be shown that in such cases, the residue number system (RNS) can become an enabling technology for realizing embedded high-end FPGA-centric DSP solutions. This thesis is developed in the context of a demonstrated RNS/FPGA synergy and the application of the new technology to communication signal processing.     

一种低复杂度的稀疏FIR陷波滤波器的设计方法

FIR陷波滤波器具有线性相位、精度高、稳定性好等诸多优势,然而当陷波性能要求较高时,通常需要较高的阶数,导致FIR陷波滤波器硬件实现复杂度大大提高。该文基于稀疏FIR滤波器设计算法和共同子式消除的思想,提出一种低复杂度的FIR陷波滤波器设计方法。该方法首先采用稀疏滤波器设计算法得到满足频域性能设计要求的FIR陷波原始滤波器系数,然后对其进行CSD编码,并分析CSD编码量化系数集中所有的2项子式和孤子的灵敏度,最后根据灵敏度的大小依次选择合理的2项子式或孤子直接合成滤波器系数集。仿真结果表明,新算法设计实现的FIR陷波滤波器比已有的低复杂度设计方法最多可减少51%的加法器,有效地降低了硬件实现复杂度,大大节省了硬件资源。     

Modified Metaheuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters

Reconfigurable non-uniform channel filters are now being widely used in software define radio (SDR). The hardware implementation of these filters requires low complexity, low chip area and low power consumption. The frequency response masking (FRM) approach is proved to be a good candidate for the realization of a sharp digital finite impulse response (FIR) filter with low complexity. To reduce the complexity further, this paper gives an optimal design method which makes the channel filters totally multiplier-less. This is done in two steps. The channel filters are designed using the FRM approach with continuous filter coefficients. To obtain multiplier-less design, these filter coefficients are converted to finite-precision coefficients using signed power of two (SPT) space and the filter coefficients are synthesized in the canonic signed-digit (CSD) format. But this may lead to degradation of the filter performance. Hence the filter coefficients synthesis in the CSD format is formulated as an optimization problem. Several meta-heuristic algorithms like Differential Evolution (DE), Artificial Bee Colony (ABC), Harmony Search Algorithm (HSA) and Gravitational Search Algorithm (GSA) are modified and deployed and the best one is selected.     

Design of FIR filter ISOTA with the aid of genetic algorithm

The field of digital signal processing has been receiving justified attention over the years because of a number of reasons including sophisticated algorithms, high computational speed and wider area of applications. In connection to this, design of finite impulse response (FIR) filter has drawn the attention of researchers throughout the globe. A number of promising developments has been carried out over the last few decades which emphasize on the design of hardware efficient filter structure. In this paper, a new technique of FIR filter design has been addressed by virtue of genetic algorithm. Filter coefficients have been searched over the discrete space in such a way that the architecture consists of shifts and only two adders. As a matter of fact, the proposed FIR filter involving shift and only two additions (ISOTA) results in minimal hardware cost during its implementation. This has been illustrated by means of a few example filters in this work. Some of the recently proposed FIR ISOTA filters have also been taken for the purpose of comparison. Finally, the proposed filter has been implemented on Altera Cyclone IV FPGA board.     

Higher order Σ-Δ modulation encoding for design ofmultiplierless FIR filters

A technique is presented for the design of multiplierless FIR filters with canonical signed digit (CSD) coefficients based on higher-order Σ-Δ modulation with a CSD quantiser (Σ-Δ-CSD). The proposed algorithm requires little computational resources and is capable of designing more types of filters and providing better performance than the previously proposed first-order method     

Design,evaluation and fault-tolerance analysis of stochastic FIR filters

Stochastic computing utilizes compact arithmetic circuits that can potentially lower the implementation cost in silicon area. In addition, stochastic computing provides inherent fault tolerance at the cost of a less efficient signal encoding. Finite impulse response (FIR) filters are key elements in digital signal processing (DSP) due to their linear phase-frequency response. In this article, we consider the problem of implementing FIR filters using the stochastic approach. Novel stochastic FIR filter designs based on multiplexers are proposed and compared to conventional binary designs implemented using Synopsys tools with a 28-nm cell library. Silicon area, power and maximum clock frequency are obtained to evaluate the throughput per area (TPA) and the energy per operation (EPO). For equivalent filtering performance, the stochastic FIR filters underperform in terms of TPA and EPO compared to the conventional binary design, although the stochastic design shows more graceful degradation in performance with a significant reduction in energy consumption. A detailed analysis is performed to evaluate the accuracy of stochastic FIR filters and to determine the required stochastic sequence length. The fault-tolerance of the stochastic design is compared with that of the binary circuit enhanced with triple modular redundancy (TMR). The stochastic designs are more reliable than the conventional binary design and its TMR implementation with unreliable voters, but they are less reliable than the binary TMR implementation when the voters are fault-free.     

Power-efficient FIR filter architecture design for wireless embedded system

This paper presents a novel approach for implementing power-efficient finite-impulse response (FIR) filters that requires less power consumption than traditional FIR filter implementation in wireless embedded systems. The proposed schemes can be adopted in the direct form FIR filter and achieve a large amount of reduction in the power consumption. By using a combination of proposed methods, balanced-modular techniques with retiming and separated processing data-flow scheme with modified canonical signed digit (CSD) representation, experimental results show that the proposed scheme reduce 76% power consumption of the original direct-form structure with slight area overhead.     

基于FPGA的直接型FIR滤波器实现

FIR滤波器在数字通信系统中被大量使用,对其进行研究具有重要的意义。先对3种基本结构的FIR滤波器进行研究,说明直接型FIR滤波器使用的存储单元最少。接着给出了直接型FIR滤波器的实现原理框图,并分别对ROM单元和MAC单元模块所采用的实现方法占用存储单元和时钟频率进行具体比较,得出较优的直接型FIR滤波器的FPGA实现方案和框图。最后通过仿真验证了各模块的功能。此实现方案具有比较高的设计效率和推广应用价值。     

窄带低通滤波的FPGA实现

文中介绍两种滤波器设计方法,一种为內插级联滤波器,另一种为多抽样率滤波器,这两种方法可以实现过渡带极窄的低通滤波器,在中频直接采样的信号处理中,可以解决提取窄带信号的问题;将这两种方法加以仿真比较,在采用FPGA实现时,内插级联滤波器大大减少了窄带低通滤波器设计所需的乘法器。     

Interpolated narrowband lowpass FIR filters

The article describes a class of digital filters, called interpolated finite impulse response (IFIR) filters that can implement narrowband lowpass FIR filter designs with a significantly reduced computational workload relative to traditional FIR filters. Topics discussed include: optimum expansion factor choice, number of FIR filter taps estimation, IFIR filter performance modeling, passband ripple considerations, implementation, and filter design.     

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.     

FIR滤波器的DSP实现

介绍了FIR滤波器的基本结构及设计方法,结合实例,给定滤波器的数字指标。利用FDATool来确定FIR滤波器抽头系数。基于DSP平台,采用MATLB产生待滤波输入信号导入到用C语言实现的FIR低通滤波器中,并且在CCS上仿真,对仿真结果与理论值进行比较。波形仿真结果和理论值相吻和表明设计的系统是正确、稳定的。不同的应用场合,FIR滤波器要求有不同性能,只要修改本设计中滤波器的系数,就可以实现性能不同的FIR滤波器。     

Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension

This paper presents four novel area-efficient field-programmable gate-array (FPGA) bit-parallel architectures of finite impulse response (FIR) filters that smartly support the technique of symmetric signal extension while processing finite length signals at their boundaries. The key to this is a clever use of variable-depth shift registers which are efficiently implemented in Xilinx FPGAs in the form of shift register logic (SRL) components. Comparisons with the conventional architecture of FIR filter with symmetric boundary processing show considerable area saving especially with long-tap filters. For instance, our architecture implementation of the 8-tap low Daubechies-8 FIR filter achieves ~ 30% reduction in the area requirement (in terms of slices) compared to the conventional architecture while maintaining the same throughput. Two of the above-cited novel architectures are dedicated to the special case of symmetric FIR filters. The first architecture is highly area-efficient but requires a clock frequency doubler. While this reduces the overall processing speed (to a maximum of 2), it does maintain a high throughput. Moreover, this speed penalty is cancelled in bi-phase filters which are widely used in multirate architectures (e.g., wavelets). Our second symmetric FIR filter architecture saves less logic than the first architecture (e.g., 10% with the 9-tap low Biorthogonal 9&7 symmetric filter instead of 37% with the first architecture) but overcomes its speed penalty as it matches the throughput of the conventional architecture.