Thin nitride films on textured polysilicon to increase multimegabitDRAM cell charge capacity

A technique for increasing the charge storage capacity of advanced multimegabit dynamic RAMs (DRAMs) up to 34% without changing the cell area or dielectric thickness is discussed. The technique does not require an additional masking step. A polysilicon texturing process is combined with a dielectric which has bulk-limited electrical conduction. The leakage current is not affected by this process, and the field acceleration coefficient is considerably increased     

Piezoresistance in polysilicon

A theoretical model for piezoresistance in polysilicon is described. Grain size, orientation and doping dependence effects are included. Predictions of gauge factor using the model give reasonable agreement with experimental results and enable optimum processing parameters to be chosen for a given grain size.     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

Tenth-micron polysilicon thin-film transistors

Small thin-film polysilicon transistors are of interest for load devices in static random-access memory (SRAM) cells of the near future. We present measured characteristics of thin-film transistors (TFT's) with gate lengths ranging from 7 to 0.12 μm made in large-grain polysilicon     

Characterization of polysilicon oxides thermally grown anddeposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q_bd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide     

增加折叠电流保护的电路

对许多需要数安培供电电流的应用而言，三端输出可调线性稳压器有易用．低成本和完全片上过载保护等特点，如美国国家半导体公司的LM317。增加数个元器件可以使三端稳压器具备一种高速度的短路限流能力，从而提高可靠性。限流器可将最大输出电流限制在一个安全的恒定水平IMAX上，避免稳压器的损坏。当出现一个故障状况时，传输晶体管上的功耗近似于VIN&#215;IMAX。要让设计的稳压器能承受过载，就需要谨慎地选择元器件的额定值（经常是留了过大的余地），除非可以在故障发生时降低或折叠（foldback）输出电流。     

Superbeta polysilicon emitter transistors

In-situ phosphorus-doped polysilicon emitters deposited on monocrystalline silicon substrates at a temperature of 627°C and subjected to no additional high-temperature annealing are shown to be capable of giving Gummel numbers GEin excess of 10¹⁵scm^-4. Polysilicon emitters formed in this way have been used to produce superbeta transistors with performance comparable to the record levels recently reported for MIS emitter devices. In particular, common-emitter current gains β in excess of 30000 have been obtained at low VCBvalues.     

Control of boron diffusion in polysilicon for constructing overlapping polysilicon gate charge-coupled devices

The diffusion coefficient of boron having values significantly different in silicon and silicon dioxide has been used to control the doping of boron impurity in intrinsic polysilicon deposited over the gate oxide. The method reduces the possibility of doping gate oxide while diffusing boron in polysilicon. Using the method, silicon gate p-MOSFETS and twenty bit photo-sensor, four phase, double overlapping polysilicon gate surface channel charge-coupled devices have been constructed with a transfer efficiency of 0.9990. The measured values of the threshold voltage of MOSFETS are in close agreement with their corresponding calculated values.     

Solar cells from polysilicon rods

The photovoltaic properties of p?n junctions made from 1-pass zone melting polycrystalline silicon rods are presented. This solution is considered as an intermediate step for similar cells, but from semielectronic grade polysilicon material. Efficiencies of up to 5.6% have been obtained, even without antireflection coatings.     

Recessed polysilicon encapsulated local oxidation

Local oxidation of silicon (LOCOS) is the most commonly used isolation technology in silicon integrated circuits. The inherently large field oxide encroachment associated with LOCOS severely limits scalability. Recessed polysilicon encapsulated local oxidation (recessed PELOX) is demonstrated to achieve both low encroachment and increased field oxide recess. These benefits are obtained without sacrificing process simplicity or defectivity as evidenced by excellent gate oxide and diode quality     

SOI-CMOS devices on beam-recrystallized polysilicon

Control of the grain boundary direction in the recrystallized polycrystalline silicon (polysilicon) island is achieved by the direction of the laser scanning. By using this technique, the source-to-drain short in a short-channel MOSFET is almost eliminated, and MOSFETs with channel lengths of 2–3 μm level in both n-channel and p-channel mode are fabricated with a good uniformity and reproducibility.The low-field electron and hole mobilities are 580 cm²/Vsec and 220 cm²/Vsec, respectively.19-stage CMOS ring oscillators with nominal channel lengths of 3μm are fabricated. The minimum propagation delay is 280 psec/stage at a supply voltage of 10 V, and the minimum power delay product is 0.13 pJ/stage.     

Disposable polysilicon LDD spacer technology

An advanced 0.5-μm CMOS disposable lightly doped drain (LDD) spacer technology has been developed. This 0.5-μm CMOS technology features surface-channel LDD NMOS and PMOS devices, n⁺/p⁺ poly gates, 125-A-thick gate oxide, and Ti-salicided source/drain/gate regions. Using only two masking steps, the NMOS and PMOS LDD spacers are defined separately to provide deep arsenic n⁺ regions for lower salicided junction leakage, while simultaneously providing shallow phosphorus n^- and boron p^- regions for improved device short-channel effects. Additionally, the process allows independent adjustment of the LDD and salicide spacers to optimize the LDD design while avoiding salicide bridging of source/drain to gate regions. The results indicate extrapolated DC hot-carrier lifetimes in excess of 10 years for a 0.3-μm electrical channel-length NMOS device operated at a power-supply voltage of 3.3 V     

High-gain SOI polysilicon emitter transistors

The authors report the first high-gain polysilicon emitter bipolar transistors fabricated on zone-melting-recrystallized (ZMR) silicon-on-insulator (SOI) material. Current gains as high as 230 were obtained. Polysilicon emitter bipolar transistors made on bulk silicon wafers with identical and simultaneous heat treatments show significant differences in emitter resistance and DC characteristics as compared with SOI bipolar transistors. Post-metal anneal improves the current gain and base current ideality at low base-emitter voltages for both types of wafers     

A true polysilicon emitter transistor

A polysilicon emitter transistor has been fabricated in which the metallurgical base/emitter junction coincides with the interface between polycrystalline and monocrystalline material. The emitter region was formed by deposition of heavily phosphorus-doped polysilicon in an LPCVD reactor at 627°C, a temperature low enough to prevent diffusion of phosphorus into the substrate. Emitter Gummel numbers of over 10¹⁴scm^-4have been obtained with this structure, allowing common emitter current gains in excess of 10000 to be reached for base implant doses of 10¹²cm^-2.     

High-performance laser-processed polysilicon thin-film transistors

We present electrical results from hydrogenated laser-processed polysilicon thin-film transistors (TFT's) fabricated using a simple four-mask self-aligned aluminum top-gate process. Transistor field-effect mobilities of 280-450 cm²/Vs and on/off current ratios of more than 10⁸ are measured in these devices. Except for the amorphous-silicon deposition step, the highest processing temperature that the substrate was subjected to was 350°C. Such good performance is attributed to an optimized laser-crystallization process combined with hydrogenation     

A polysilicon emitter solar cell

A new solar cell structure is reported in which the emitter consists of a thin layer of in situ phosphorus-doped polysilicon deposited by a low-pressure chemical vapor deposition (LPCVD) techniques. The highest process temperature required to fabricate this structure is only 627°C. Although the use of a polysilicon emitter results in some degradation in blue response, both theoretical and experimental results are presented indicating that photocurrent densities in excess of 30 mA.cm^-2are attainable under AM1 illumination. The low back-injection current associated with the polysilicon emitter has allowed a very high open circuit voltage of 652 mV to be obtained at 28°C in a cell illuminated to give a short circuit current density of 30 mA.cm^-2.