Computer-aided performance assessment of fully depleted SOI CMOSVLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies     

Floating-body effects in partially depleted SOI CMOS circuits

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for     

A floating-body charge monitoring technique for partially depleted SOI technology

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents.     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

Substrate current measurements in thin SOI MOSFET's at 300 and 77 K

Measurements of impact-ionized hole current in fully depleted SOI (silicon-on-insulator) MOSFETs at room temperature and liquid nitrogen temperature are reported. The measured current exhibits properties similar to those of the substrate current in bulk transistors, except for higher drain biases when the parasitic bipolar in the device is significant. Since the body contact is effective in collecting only a small fraction of the total generated hole current, the body contact cannot be used to eliminate the bipolar action in thin SOI, at least for channel widths on the order of 10 μm     

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power Mixed Digital/Analog/Microwave Circuits

This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.     

Integrated sensor and electronic circuits in fully depleted SOItechnology for high-temperature applications

The electrical characteristics of devices and circuits realized in CMOS technology on silicon-on-insulator (SOI) substrates and operated at elevated temperatures are presented and compared with results obtained using other materials (bulk Si, GaAs, SiC). It is demonstrated that fully depleted CMOS on SOI is the most suitable process for the realization of complex electronic circuits to be operated in high-temperature environments, up to more than 300°C     

Fault tolerant system based on IDDQ testing

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.     

High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling

Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100/spl deg/C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.     

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm² silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test     

SOI横向栅控双极晶体管特性研究

横向SOI双极技术具有工艺简单、寄生电容小等优势,被认为是射频领域最有希望的技术之一。为了得到可用于射频领域的SOI横向栅控双极晶体管特性,采用一种SOI横向栅控双极晶体管器件结构,研究范围包括工艺实现过程和器件性能特性。实验表明,该器件工艺与平面CMOS工艺完全兼容,通过对栅端电压的控制,可以实现hFE在一个较大的范围内自由调节,具有更大的使用灵活性。     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。     

PD/SOI SRAM performance in presence of gate-to-body tunneling current

This paper presents a detailed study on the effects of gate-to-body tunneling current on partially depleted silicon-on-insulator (PD/SOI) CMOS SRAM. It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations. The degradation in the "write" performance is shown to be more significant than the degradation in the "read" performance, and the effect is more pronounced at lowered temperature. For the beneficial side, the presence of the gate-to-body tunneling current reduces the initial cycle parasitic bipolar disturb from unselected cells on the same bitline during write/read operation.     

Analysis and control of floating-body bipolar effects in fullydepleted submicrometer SOI MOSFET's

Floating-body effects triggered by impact ionization in fully depleted submicrometer silicon-on-insulator (SOI) MOSFETs are analyzed based on two-dimensional device simulations. The parasitic bipolar junction transistor (BJT) effects are emphasized, but the kink effect and its disappearance in the fully depleted device are first explained physically to provide a basis for the BJT analysis. The results of simulations of the BJT-induced breakdown and latch phenomena are given, and parametric dependences are examined to give physical insight for optimal design. The analysis further relates the DC breakdown and latch mechanisms in the fully depleted submicrometer SOI MOSFET to actual BJT-related problems in an operating SOI CMOS circuit. A comprehensive understanding of the floating-body effects is attained, and a device design to control them utilizing a lightly doped source (LDS) is suggested and shown to be feasible     

ESD reliability and protection schemes in SOI CMOS output buffers

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate.<>     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

全耗尽CMOS／SOI技术的研究进展

ＳＯＩ材料技术的成熟，为功耗低，抗干扰能力强，集成度高，速度快的ＣＭＯＳ／ＳＯＩ器件的研制提供了条件，分析比较了ＣＭＯＳ／ＳＯＩ器件与体硅器件的差异，介绍了国外薄膜全耗尽ＳＯＩ技术的发展和北京大学微电子所的研究成果。     

Parasitic bipolar gain reduction and the optimization of 0.25-μmpartially depleted SOI MOSFETs

An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-μm partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, and germanium implantation on the lateral bipolar gain are characterized for optimal performance and manufacturability. Channel doping has the expected impact on bipolar gain. Silicide proximity is shown also to have a large impact. Germanium implantation into the source/drain regions reduces the lateral bipolar gain due to the introduction of defects that act as recombination centers in the source, reducing emitter efficiency. Further, germanium implantation serves to finely control the silicidation process, leading to good manufacturing control of the lateral silicide encroachment. Analysis of MOSFET dc I-V characteristics shows that threshold voltages for SOI have to be set only 30-50 mV higher for comparable dc off current to bulk CMOS. Finally, the impact of bipolar gain on floating-body-induced hysteretic effects and on alpha-particle-induced SRAM soft error rates are described