基于POOSL的系统性能建模与性能分析

本文介绍了面向对象的并行描述语言(POOSL,ParallelObject-OrientedSpecificationLanguage)的基本语义语法及相关的建模工具,并通过对一个基本的包交换系统的建模和分析,说明了利用POOSL进行软硬件系统的性能建模和性能分析的基本方法。     

The design and simulation of a multi-computer network message processor

This paper describes a simulation language and its application to the design of a multicomputer network message processor. The language, called OASIS, provides a programming environment which facilitates the development of distributed software. Modular software, computer system hardware models, and the simulated execution of this software by the hardware models can be defined within OASIS. The network message processor supports bidirectional data transmission among terminals, host computers, and other network message processors. A modular design of this network message processor is implemented by a local network of five microcomputers communicating over a time shared bus. In this paper, OASIS is used to develop system software before network message processor hardware is available.     

基于SystemC和POOSL的语音识别系统的系统级建模与性能分析的对比*

根据复杂嵌入式系统的系统级建模的需要,提出了一套复杂嵌入式系统的系统级设计流程和建模方法。该方法主要包括了层次化建模方法、TopDown建模方法、面向对象建模技术和YChart建模方法,并采用提出的系统级建模方法,分别使用SystemC语言和POOSL语言成功地对语音识别系统进行了建模;通过模型的仿真进行了性能分析,并对分别得到的性能分析结果进行了对比,两种语言的系统延迟时间与CPU占用率的性能分析结果基本一致,为建模人员进行复杂嵌入式系统的系统级建模和性能分析提供了指导与参考。     

基于ARM-WinCE的某型航空发动机温控盒检测仪设计

提供了一种基于ARM处理器、Windows CE嵌入式操作系统的检测仪设计方案,介绍了软硬件设计。软件设计中,定制了操作系统,编写了硬件驱动程序,利用多线程技术实现了检测数据的实时显示,同时具有数据保存、故障分析等功能,得出了待测方波频率与测量时机的基本关系。试验结果表明,该检测仪稳定性好、精度高、操作简单,设计思想和工程实现方法对低频方波信号的物理量实时检测具有一定的借鉴意义。     

Design methodology for a modular service-driven network processor architecture

We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system.     

QuePED: Revisiting queueing networks for the performance evaluation of database designs

Databases form the common component of many software systems. However, performance models specifically targeted at the database design have not been extensively studied. In this paper, we propose QuePED – a queueing network performance evaluation model for database designs. QuePED provides for the performance modelling of database design constructs, including active database rules; thus, deviating from current methods that consider database designs as processing demands on the hardware architecture. We present a formal specification of QuePED and describe its application to database designs. Experimental evaluation has shown the ability of QuePED to capture the steady state performance of an implementation of the TPC-C benchmark.     

Fail-Awareness: An Approach to Construct Fail-Safe Systems

We present a framework for building fail-safe hard real-time applications in timed asynchronous distributed systems subject to communication partitions and performance, omission, and crash failures. Most distributed systems built from commercial-off-the-shelf (COTS) processor and communication services are subject to such partitions because their COTS components do not provide hard real-time guarantees. Also custom designed systems can be subject to partitions due to unmaskable link or router failures. The basic assumption behind our approach is that each processor has a local hardware clock that proceeds within a linear envelope of real-time. This allows one to compute an upper bound on the actual delays incurred by a particular processing sequence or message transmission. Services and applications can use these computed bounds to detect when they cannot guarantee all their standard properties because of excessive delays. This allows an application to be fail-aware, that is, to detect when it cannot guarantee all its safety properties and in particular, to detect when to switch to a fail-safe mode.     

SystemJ: A GALS language for system level design

In this paper we present the syntax, semantics, and compilation of a new system-level programming language called SystemJ. SystemJ is a multiclock language supporting the Globally Asynchronous Locally Synchronous (GALS) model of computation. The synchronous reactive (SR) model is used for synchronous parts of the modelled system, and those parts, which represent individual clock-domains, are coupled asynchronously each to the other on the top-level of system design. SystemJ is based on Java language, which is used to describe “instantaneous” data transformations. Hence, SystemJ is well suited for both software-based embedded and distributed systems. SystemJ offers effective modelling of (1) data transformations through the power of Java, (2) control and synchronous concurrency through the SR paradigm and (3) asynchronous concurrency through clock domains and rendezvous. The language is based on semantics that is amenable to efficient code generation and partial automatic verification. The SystemJ micro-step semantics provide asynchronous and synchronous extensions over the semantics of other SR languages such as Esterel and provide an ideal platform for efficient software implementation.     

Task management in Ada—A critical evaluation for real-time multiprocessors

As the cost of processor hardware declines multiprocessor architectures become increasingly cost-effective and represent an important area for future research. In order to exploit the full potential of multiprocessors, however, it is necessary to understand how to design software which can make effective use of the available parallelism. This paper considers the impact of multiprocessor architecture on the design of high-level programming languages and, in particular, evaluates the language Ada in the light of the special requirements of realtime multiprocessor systems. We conclude that Ada does not, as currently designed, meet the needs for real-time embedded systems.     

基于ARM-WinCE的电动投弹控制器检测研究

提出了一种基于ARM处理器、WinCE嵌入式系统的电动投弹控制器检测仪设计方案,介绍了软硬件设计.软件设计中,定制了操作系统,开发了硬件驱动程序和采用多线程并行处理技术的应用程序,实现了检测数据的实时显示、数据保存、故障诊断等功能,有效检测了电动投弹控制器的工作状态.结果表明,该检查仪稳定性好、精度高,设计思想和工程实现方法对低频脉冲信号的物理量实时检测具有借鉴意义.     

SNAPL/1: A language to describe and evaluate queuing network models

Recent theoretical developments in queuing theory have made multiclass queuing network models a viable alternative to established simulation methods for the analysis of dynamic systems. Computer software is required to describe and solve such network models. This paper describes a language which provides the human interface to a particular multiclass queuing network modelling package. The discussion is illustrated with an example from the language and concludes with suggestions for improvements.     

嵌入式MPEG4视频服务器设计和实现

本文提出并设计嵌入式MPEG4视频服务器视频监控系统,以双核嵌入式处理器BF561为硬件平台,搭建一个网络可访问的流媒体服务器系统。该服务器至少提供5个远程用户的网络登陆和视频图像的实时传输,同时,详细地论述了系统设计方案,硬件和软件方面的设计,并给出实际运行结果。     

Executable specifications for embedded distributed systems

Combining hardware components with an executable specification language facilitates the specification prototyping of embedded distributed systems. The specification language should cover process management, timing, and communication commands that real-time executive and communication task services of every node prototype can interpret. We use a technique that employs attribute grammars and either a macro processor or Prolog to execute the language     

基于网络处理器IXP2400系统的软件设计

网络处理器高性能的包处理能力及可编程的灵活性适应了当前网络发展需求，广泛应用于高端路由器、边缘多业务宽带接入、媒体网关和安全等领域。基于网络处理器成功构建一个网络系统的关键在于网络处理器软件系统的设计与开发，其核心问题就是要软件系统充分发挥网络处理器灵活性和高性能的特点，面向网络处理器的硬件体系结构编程，合理利用网络处理器，为优化数据包处理的各种硬件资源设计高效的多处理器、多线程并行机制。本文以网络处理器IXP2400实现高速网络应用为例，介绍基于网络处理器系统的软件开发过程和设计方法，探讨开发高性能的微码软件的策略和技术。首先介绍了基于网络处理器系统的硬件体系结构配置和软件开发框架、应用软件的系统分析和总体设计，着重分析了基于网络处理器系统的多微引擎、多线程的并行处理机制，以及互斥问题和包排序问题的解决方法，最后讨论了系统的性能评估方法。