Chaos in pulse-excited resonator with self feedback

A novel nonautonomous chaotic oscillator based on an active series LC resonator is reported. Excitation is provided by a bipolar pulse-train voltage-source and self feedback via a comparator is employed. The high-dimensional nature of the oscillator is clarified.     

高共模输入电平的迟滞比较器设计

提出了一种新颖的基于双极工艺的迟滞比较器,该电路在保持了传统电路的高共模输入电平和低功耗的优点的同时,在电路结构上比传统的电路节省了一级射随器。此外,为了保证该迟滞比较器中两级运算放大器的稳定性还进行了频率补偿的研究,并对该电路的稳定性进行了仿真,其仿真结果保证了60°的相位裕度。该迟滞比较器的电路使用华润上华1μm双极晶体管工艺实现,芯片测试结果表明,其上阈值点为7.4 V,下阈值点为6.92 V,迟滞电压约为0.48 V,输出高电平约为0.76 V,电路工作稳定。     

具有带隙结构的迟滞比较器电路设计

基于LED驱动的微功耗DC—DC转换器,针对低压高稳定性的要求设计了一款具有带隙结构的迟滞比较器电路,它的最低输入电压为1．2V,其核心电路有带隙基准比较器、射极跟随器和迟滞比较器。整个电路采用Bipolar工艺设计,利用HSpice软件对所设计的电路进行了仿真与验证。结果表明,迟滞比较器的迟滞电压为8mV,翻转门限电压随输入电压和温度的变化均很小。     

一种有源电压限位电路的设计

本文提出了一种新颖的电压限位电路。该电路该采用电压跟随器FOLLOWER和模拟二选一选择器结构,其中的比较器采用PNP双极型三极管,从而使输出更精确地跟随输入。与传统电压限压电路相比,该电路在设定的电压范围内,输出电压能更好地跟随输入电压变化,在输出端误差小,设定的电压范围以外,电路输出能固定在某一特定值。本电路基于0.35 um BCD工艺,对所设计电路进行了仿真验证。仿真结果表明,当下限阈值VTH-设定在0.5V,上限阈值VTH+设定在2V,输入电压VIN输入范围在0~3V内时,输出电压精确跟随VIN的变化而变化。     

High-speed, highly sensitive OEIC using clocked vertical BJT'sphotoDarlington in CMOS technology

A novel CMOS synchronized photoreceiver is proposed for conversion of optical input pulses to digital output signals. The photoreceiver circuit consists of a photoDarlington used as a detector of input light followed by a current-mirror comparator used as a converter to electronic signals. A combination of two p-n-p vertical CMOS bipolar junction transistors controlled by an external clock is designed to achieve the first clocked photoDarlington structure. The generated photocurrent is amplified and digitized by the current-mirror comparator in a return to-zero format. The synchronized photoreceiver has been implemented in a standard digital 0.7 μm, 5 V n-well CMOS technology with an effective area of 100×60 μm². It was measured to operate at 100 MHz with an external input light of 13.3 fJ/pulse (-18.8 dBm/beam)     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

A fast, latching comparator for 12 bit A/D applications

High-speed, 12 bit accurate successive approximation A/D converters demand a comparator with both excellent input specifications and fast response time. The author describes a voltage comparator with 50 ns response time to 1/2 LSB overdrive (1.2 mV) and 0.1 LSB (250 /spl mu/V) total input error. Unique features of the circuit include a super-/spl beta/ input stage, a fast buried-zener level-shift, a fully differential output stage, a floating-zener biasing scheme, and a fast latch circuit which does not interfere with input accuracy. The comparator is manufactured on a bipolar, double-implanted, thin epi, junction-isolated process.     

Two-stage chaotic Colpitts oscillator

A novel version of the chaotic Colpitts oscillator is proposed. It contains two bipolar junction transistors coupled in series. The resonance loop consists of an inductor and three capacitors. The two-stage oscillator, compared with the classical circuit, enables the fundamental frequency of chaotic oscillations to be increased by a factor of three. The PSpice simulations performed with 9 GHz threshold frequency transistors demonstrate that the highest fundamental frequencies of chaotic behaviour are 1 and 3 GHz for the classical and the two-stage Colpitts oscillator, respectively     

基于文氏振荡器的忆阻混沌电路

该文采用文氏桥振荡器和磁通控制的分段线性忆阻器,设计了一种新的单一参数控制的混沌电路。通过调节控制参数,该系统在忆阻器的非线性作用下,通过倍周期分岔产生了混沌和超混沌现象。利用常规的动力学分析手段研究了电路参数变化时系统的动力学特性,例如平衡点稳定性分析,李雅普诺夫指数谱和分岔图。为了验证电路的正确性,该文采用集成运放和压控开关实现了一个分段线性磁控忆阻器的模拟等效电路,并将该系统应用于提出的混沌电路,Pspice仿真结果与理论分析完全吻合。     

一种单片高速八位A／D转换器的设计

本文介绍了一种硅双极型单片大规模集成8位逐次近似A/D转换器X1001的电路设计,这种电路采用了自锁式电压比较器和高速低功耗ECL逻辑电路,转换时间为400ns,是单片集成逐次近似A/D转换器中速度最快的器件。     

一种基于闩锁结构的高速电压比较器

文章结合高速A/D转换器的研究设计了一种新型高速、高精度集成闩锁比较器,针对提高集成闩锁型电压比较器的性能,讨论了比较器失效、速度-功耗优化、时钟反馈噪声等设计问题.该比较器有较高的输入电阻,对高频时钟的反馈噪声有较好的抑制性能,采用"电容中和技术"补偿预放大级带宽后更加适用于高速应用的需要.文中给出了详细的性能分析以及采用PSPICE仿真的模拟结果.     

A fast latching current comparator for 12-bit A/D applications

Describes a novel monolithic high-speed comparator which senses the polarity of the input current rather than voltage. The new approach greatly reduces overall system conversion time for a successive approximation 12-bit A/D converter. The circuit features a single input pin for polarity discrimination, dual complementary outputs, and fast response time of 72 ns to 0.5 LSB overdrive (500 nA). The sum of the total error due to the comparator is 0.2 LSB with respect to the input. The comparator is manufactured on a bipolar, ion-implanted base, 9 /spl mu/m epi, junction-isolated process.     

A low-power low-offset dynamic comparator for analog to digital converters

A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with exhaustive Monte-Carlo simulations at various corner cases of the process. A comparison between typical comparator and the proposed comparator in 180 nm and 90 nm has been made. The power consumption of the proposed comparator is about 44% of the conventional and its offset voltage is at least one-third of other mentioned conventional comparators.     

A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion

This paper presents a monolithic comparator implemented in a 0.5-μm SiGe heterojunction bipolar transistor (HBT) process. The SiGe HBT process provides HBT npn transistors with maximum f_T over 40 GHz and f_max over 55 GHz. The comparator circuit employs a resettable slave stage, which was designed to produce return-to-zero output data. Operation with sampling rates up to 5 GHz has been demonstrated by both simulation and experiments. The comparator chip attains an input range of 1.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 407×143 μm². The comparator is intended for analog-to-digital (A/D) conversion of 900 MHz RF signals     

一种中速高精度模拟电压比较器的设计

设计一种中速高精度模拟电压比较器,该比较器采用3级前置放大器加锁存器和数字触发电路的多级结构,应用失调校准技术消除失调,应用共源共栅结构抑制回程噪声干扰;应用数字触发电路获得高性能数字输出信号,设计采用0．35μm5VCMOS工艺实现一个输入电压2．5V、速度1MS／s、精度12位的逐次逼近型MD转换器。Hspice仿真结果表明：在5V供电电压下,速度可达20MHz,准确比较0．2mV电压,有效校准20mV输入失调,功耗约1mW。     

一种单输入控制器下的忆阻混沌同步电路设计与实现

该文提出一种在单输入控制器下基于忆阻器的混沌同步模拟电路设计及其实现方法,并将它应用于基于忆阻混沌同步的保密通信.首先,基于混沌同步理论,构建了混沌同步系统及保密通信模型,并设计实现了一种4阶压控忆阻混沌电路和混沌加密解密电路.其次,将所设计的忆阻混沌电路作为混沌驱动和响应电路,根据它们的误差系统设计了一种单输入混沌同...     

一种新的混沌调制和线性解调方法

提出一种新的用于保密通信的混沌调制和线性解调方法.发送端和接收端各有一个相同的混沌电路,将有用信号接入发送端混沌电路的线性子电路,使其对该混沌电路进行调制.调制后的混沌信号传送到接收端的混沌电路,检测该电路中某一电流或电压变量,经线性滤波器解调可恢复原始有用信号.基于这一调制、解调方法的混沌通信系统保密性强且电路简单.对两个混沌保密通信系统的仿真实验取得了满意的结果.     

Hyperchaotic spiking oscillators with periodic pulse-train input

This paper studies simple spiking oscillators with periodic pulse-train input. The circuits are piecewise linear and a normal form circuit equation is derived in order to extract essential parameters. The return map and its Jacobian matrix can be described precisely. If the input is not present, the circuits can exhibit hyperchaotic and periodic attractors. As the input is applied, the attractors can be changed into various periodic, chaotic and hyperchaotic attractors. The phenomena are characterized by Lyapunov exponents of the return map. Typical phenomena can be confirmed experimentally. These results provide basic information for analysis of bifurcation phenomena and application to pulse-coupled networks.     

一个新多涡卷混沌系统的设计及在图像加密中的应用

该文提出一种三涡卷混沌系统,首先对系统的李雅普诺夫指数、分岔图、Poincare截面图、功率谱图及平衡点稳定性等动力学特性进行了理论分析和数值仿真,结果表明该系统具有良好的动力学特性和丰富的拓扑吸引子.基于电路仿真软件Multisim研制了实验仿真电路,该电路结构简单、易于实际制作,且仿真实验与理论分析结论十分吻合,证...