一种具有片上译码/放大功能的微阵列电路及其与生物纳米系统的集成

提出了一种用SMIC 0.18μm CMOS混合信号工艺实现的全集成CMOS微阵列生物芯片,并成功地实现了其与一种新的生物纳米系统的集成.该电路实现了19μm×19μm电极的4×4(16单元)阵列,反相电极.电流模式放大器,译码电路,以及逻辑控制电路的单片集成,并能够提供-1.6～1.6V的组装电压,8bit的电位分辨率及39.8dB的电流增益,电源电压为1.8V,而失调和噪声电流分别为5.9nA和25.3pArms.在实验中,利用该电路实现了对30nm聚乙烯醇包裹的磁性粒子的片上选择性组装,并对实验结果进行了讨论,从而验证了该电路的正确性和该集成方法的可行性.     

集成混频和放大功能的低价电路

在很多应用中,频率变换级包括有一只缓冲器,最好还有一些额外的电压增益电路;一只混频器:还有一些滤波电路.可以简单地将混频器功能与放大器集成起来,从而省掉混频器前的放大器.     

集成混频和放大功能的低价电路

在很多应用中，频率变换级包括有一只缓冲器．最好还有一些额外的电压增益电路；一只混频器：还有一些滤波电路。可以简单地将混频器功能与放大器集成起来．从而省掉混频器前的放大器。有种低价的实现办法是使用一只带掉电禁用功能的放大器。当用一个方波本振驱动禁用脚时，振荡器频率的方波将输入信号倍频，发生频率变换。     

一种中频AGC放大电路的设计与实现

针对接收机对中频放大电路的要求,设计实现了一种基于宽带放大器L1590的中频AGC放大电路。在介绍L1590的基础上对其整体结构进行了详细的设计,并根据电路要求设计了跟随器输出电路及取样反馈电路,该放大电路具有增益高、AGC范围宽、负载能力强、输出幅度恒定、工作性能稳定等优点,能够满足一般接收机的使用场合。     

一种片上集成低压高精度电流检测电路

提出了一种应用于电流模PWM DC-DC转换器的片上集成电流检测电路.它利用检测电阻和检测晶体管的结合,实现电感电流的检测;同时,在I-V转换电路中,运用结构简单的电流镜连接的共栅放大器实现反馈控制.在10～600 mA电感电流范围内,都可以得到高精度的检测电流,最小检测误差为0.04%.该电路在VTHN=0.735 V、|VTHP|=0.941 V的0.5 μm 1P2M CMOS工艺条件下,电路最低工作电压为1.5 V.     

一种具有片上补偿功能的红外读出电路

针对非制冷红外探测器系统,提出了一种恒流偏置的红外读出电路（ROIC）,该电路具有衬底温度补偿功能,且可实现片上偏移非均匀性补偿。基于微测辐射热计等效电阻受目标温度、衬底温度等影响的等效模型,每个读出通道采用两个盲电阻以消除衬底温度的影响,同时使用DAC逐点调节参考电压,以完成片上偏移非均匀性补偿。该ROIC 应用到阵列大小为320×240的非制冷微测辐射热计焦平面上,已在CSMC 05MIXDDST02的0.5?m CMOS标准工艺下成功流试验片。电路测试结果表明：对于常温目标,当衬底温度变化60 K时,输出电压变化小于500 mV;经偏移非均匀性补偿后,阵列的固定图像噪声为11.8 mV。该ROIC适用于应用于复杂温度环境的高均匀性非制冷红外探测器。     

一种单片集成的光接收电路的设计

基于一种光接收器件的电路结构,利用硅基BJT工艺对光电二极管和接收电路进行了设计.通过引入辅助开关电路以及双结光电二极管,提高了输出晶体管的关断速度.测试结果显示,该光接收电路在870 nm波长下的数据速率可达到10 MBd.     

一种减小工艺参数影响的CMOS集成电流源设计方法与电路实现

本文利用Vtp提取电路、能隙基准电压源电路以及运算放大电路设计了一种电流源电路。使用CADENCE SPECTRE仿真工具进行仿真，在TSMC 0.35μm工艺的五种工艺边界条件TT、FF、FS、SF、SS)下，该电路输出电流变化小于8％，并且在同一工艺边界条件下输出电流随温度(—40～85℃)变化小于3％。     

一种单片集成压力传感器信号调理电路的设计

针对单片集成压力传感器输出幅度较小、温度漂移会引起压力精度变化等难题,提出了一种新型的信号调理电路。该电路通过两个差分放大电路和四个D/A转换器来解决单片集成压力传感器的小输出和温度漂移问题。仿真结果表明,在5V电源电压下,在0℃~85℃温度范围内,信号调理电路的最大误差可以减少到满量程输出的1.8%。     

一种单片集成压力传感器信号调理电路的设计

针对单片集成压力传感器输出幅度较小、温度漂移会引起压力精度变化等难题,提出了一种新型的信号调理电路。该电路通过两个差分放大电路和四个D/A转换器来解决单片集成压力传感器的小输出和温度漂移问题。仿真结果表明,在5 V电源电压下,在0 ℃～85 ℃温度范围内,信号调理电路的最大误差可以减少到满量程输出的1.8 %。     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.     

一种高增益低功耗的CMOS低噪声放大器

设计了一种新型的全集成的电流复用两级共源低噪声放大器,采用新型输入匹配和一个级联的级间谐振电感实现了低功耗高增益。为了降低芯片面积,两个LC并联网络代替了传统的大电感。这种新型的电流复用结构更有利于输入匹配,降低噪声和功耗。采用SMIC0.18μm RF CMOS工艺制作了一个频率为2.4GHz,噪声系数1.7dB,S11为-30dB,S22为-36dB,功率增益为23dB,反向隔离度小于-35dB,在1.8V的供电电压下仅消耗2mA。     

150Ms/s、6bit CMOS数字工艺折叠、电流插值A/D转换器

在1.2μm SPDM标准数字CMOS工艺条件下,实现6bit CMOS折叠、电流插值A/D转换器;提出高速度再生型电流比较器的改进结构,使A/D转换器(ADC)总功耗下降近30%;提出一种逻辑简单易于扩展的解码电路,以多米诺(Domino)逻辑实现.整个ADC电路中只使用单一时钟.在5V电压条件下,仿真结果为采样频率150-Ms/s时功耗小于185mW,输入模拟信号和二进制输出码之间延迟小于2个时钟周期.     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

A curvature calibrated bandgap reference with base-emitter current compensating in a 0.13/tm CMOS process

In bandgap References,the effect caused by the input offset of the operational amplifier can be effectively reduced by the utilization of cascade bipolar junction transistors(BJTs).But in modern CMOS logic processes,due to the small value of β,the base-emitter path of BJTs has a significant streaming effect on the collector current,which leads to a large temperature drift for the reference voltage.To solve this problem,a base-emitter current compensating technique is proposed in a cascade BJT bandgap reference structure to calibrate the curvature of the output voltage to temperature.Experimental results based on the 0.13 μm logic CMOS process show that the reference voltage is 1.238V and the temperature coefficient is 6.2 ppm/℃ within the range of-40 to 125 ℃.     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6+4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

200Ms/s 177mW 8位折叠内插结构的CMOS模数转换器

介绍了一个采用折叠内插结构的CMOS模数转换器,适合于嵌入式应用.该电路与标准的数字工艺完全兼容,经过改进的无需电阻就能实现的折叠模块有助于减小芯片面积.在输入级,失调平均技术降低了输入电容,而分布式采样保持电路的运用则提高了信号与噪声的失真比.该200MHz采样频率8位折叠内插结构的CMOS模数转换器在3.3V电源电压下,总功耗为177mW,用0.18μm3.3V标准数字工艺实现     

1.25Gb/s CMOS高灵敏度宽动态范围跨阻放大器

采用0.35μm CMOS工艺设计并实现了一种新的应用于1.25Gb/s光纤通信接收机的高灵敏度、宽动态范围跨阻放大器电路。引入电流注入技术提高输入管跨导、优化噪声性能、提高灵敏度。自带直流反馈实现直流消除功能,同时采用自动增益控制机制,提高动态范围。仿真结果表明,该电路具有82.02dBΩ的跨阻增益、872.7MHz的带宽、23.74kHz的低频截止频率,输入等效噪声电流为4.08pA/Hz(1/2),最大输入光信号为+3dBm(2mA),在3.3V的电源电压下,芯片功耗为43.4mW。     

A CMOS A/D Converter with Piecewise Linear Characteristic and Its Application to Sensor Linearization

A novel 8-bit CMOS A/D converter with piecewise linear characteristic is designed, implemented and tested. It can be regarded as a two-stage flash A/D converter. The resulting architecture can be applied to the linearization of nonlinear characteristics of a wide variety of sensors, just adapting the break points of the piecewise linear characteristic to get the best-fit approach to the inverse of the sensor characteristic under consideration. A very compact implementation is obtained, since two-stage A/D conversion and linearization are both performed simultaneously by the same circuit and because both A/D conversion stages share most of the required hardware. As a particular example, a sinusoidal nonlinearity, typical of several types of solid-state sensors, is compensated in this paper. Measurement results for a 2 m CMOS prototype demonstrate the validity of the proposed approach.