基于CORDIC的精确快速幅相解算方法

针对传统CORDIC算法进行高精度幅度相位解算时迭代次数过多、时延较长、相位收敛较慢等局限,提出了一种基于最佳一致逼近方法的幅度与相位补偿算法,即利用传统CORDIC算法迭代一定次数后得到的向量信息,采用最佳一致逼近方法对幅度和相位分区间进行一阶多项式补偿,有效提高了计算精度.仿真及实测结果表明,对传统CORDIC算法4次迭代后的结果进行补偿,幅度相对误差可达到10^-5量级、相位绝对误差可达到10^-5度量级,最大输出时延不大于100ns.在使用部分专用乘法器的条件下,寄存器消耗降低了42.5%,查找表消耗降低了15.5%.采用该补偿算法,每多一次CORDIC迭代其相位精度可提高约一个数量级.因此,本文提出的补偿CORDIC算法在迭代次数、计算精度等方面优于传统CORDIC算法,适合于高精度计算的场合.     

Mixed-radix,virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.     

CORDIC-based VLSI architectures for digital signal processing

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms     

Optimization of CORDIC cells in the backward circular rotation mode

The COordinate Rotation DIgital Computer (CORDIC) algorithm in the backward circular rotation mode efficiently computes phase estimation. In this letter, a set of new rules are proposed to design a CORDIC processor to achieve a given signal-to-noise ratio (SNR). To this end, two new approximate expressions to estimate the SNR are derived accounting for the approximation and quantization errors, respectively.     

Efficient CORDIC Algorithms and Architectures for Low Area and High Throughput Implementation

This paper presents two area-efficient algorithms and their architectures based on CORDIC. While the first algorithm eliminates ROM and requires only low-complexity barrel shifters, the second eliminates barrel shifters completely. As a consequence, both the algorithms consume approximately 50% area in comparison with other CORDIC designs. Further, the proposed algorithms are applicable to the entire range of angles. The FPGA implementations consume approximately 8% LUTs of a Xilinx Spartan XC2S200E device and have a slice-delay product of about 3. Convergence proofs for the algorithms are presented. Experimental comparisons with prior CORDIC designs confirm the efficacy of the proposed designs.      

CORDIC instructions for LDPC decoding on SDR platforms

Wireless protocols strive to increase spectral efficiency and achieve high data throughput. Low-density parity-check (LDPC) codes are advanced forward error correction (FEC) codes that use iterative decoding techniques to achieve close to the Shannon capacity. Due to their superior performance, state-of-art wireless protocols, such as WiMAX and LTE Advanced, are adopting LDPC codes. LDPC codes come with the high cost of drastically increased computational effort for decoding. Among the proposed decoding algorithms, the belief propagation (BP) algorithm leads to a good approximation of an optimal decoder; however, it uses compute-intensive hyperbolic trigonometric functions. To reduce the computational complexity, typical LDPC decoder implementations use simplified algorithms, such as the min-sum algorithm, at the expense of reduced signal processing performance. Efficient and accurate methods to compute hyperbolic trigonometric functions can facilitate the use of the BP algorithm in real-time LDPC decoder implementations. This paper investigates hyperbolic COordinate Rotation DIgital Computer (CORDIC) instruction set architecture (ISA) extensions for software-defined radio (SDR) processors to compute the hyperbolic trigonometric functions for LDPC decoding efficiently. The CORDIC ISA extensions are evaluated on the low-power multi-threaded Sandbridge Sandblaster? SB3000 platform. The computational performance, numerical accuracy, hardware estimates, power consumption estimates, and memory requirements with the CORDIC ISA extensions are compared to a baseline implementation without these extensions on the SB3000.     

An efficient design of CORDIC in Quantum-dot cellular automata technology

Power dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.     

Application of Reconfigurable CORDIC Architectures

Reconfiguration enables the adaption of Coordinate Rotation DIgital Computer (CORDIC) units to the specific needs of sets of applications, hence creating application specific CORDIC-style implementations. Reconfiguration can be implemented at a high level, taking the entire CORDIC unit as a basic cell (CORDIC-cells) implemented in VLSI, or at a low level such as Field-Programmable Gate Arrays (FPGAs). We suggest a design methodology and analyze area/time results for coarse (VLSI) and fine-grain (FPGA) reconfigurable CORDIC units. For FPGAs we implement CORDIC units in Verilog HDL and our object-oriented design environment, PAM-Blox. For CORDIC-cells, multiple reconfigurable CORDIC modules are synthesized with state-of-the-art CAD tools. At the algorithm level we present a case study combining multiple CORDICs based on a geometrical interpretation of a normalized ladder algorithm for adaptive filtering to reduce latency and area of a fully pipelined CORDIC implementation. Ultimately, the goal is to create automatic tools to map applications directly to reconfigurable high-level arithmetic units such as CORDICs.     

Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC

Fast Fourier transform (FFT) accelerator and Coordinate rotation digital computer (CORDIC) algorithm play important roles in signal processing.We propose a conflgurable floating-point FFT accelerator based on CORDIC rotation,in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory.To finish CORDIC rotation efficiently,a novel approach in which segmentedparallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration.To prove the efficiency of our FFT accelerator,four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT.Experimental results show that our structure,which is composed of four butterfly units and finishes FFT with the size ranging from 64 to 8192 points,occupies 33230(3％) REGs and 143006(30％)LUTs.The clock frequency can reach 122MHz.The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4.What's more,only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.     

字长可重构流水线CORDIC设计

设计了一种数据字长可重构的流水线坐标旋转数字计算(Coord inate R otation D ig ita l Com pu ting,CORD IC)单元,用于可重构DSP阵列式处理引擎的处理单元核心的设计。首先对流水线CORD IC的模校正进行改造,使流水级数有所减少,且使模校正流水的分配有利于字长可重构的设计。之后通过相邻8位流水线CORD IC单元间的横向和纵向可重构设计,使相邻的(2×2)/(3×3)/(4×4)个基本单元可以组合成数据字长为16/24/32位的CORD IC单元。     

去除地面反射波的波达角估计方法研究

以基于极化平面的波达角（Direction of Arrival，DOA）估计算法为基础，针对近地面天线受地面反射波影响从而极大地影响DOA估计的准确性问题，对如何去除地面反射波的影响进行深入研究.分别采用理想地面近似法、反射系数法和阵列抑制算法进行仿真试验，对比和分析这三种算法的优缺点，以及各自的适用性.理论分析和仿真试验表明:理想地面近似算法在实际地面参数与理想导电平面相近时，具有准确的计算结果，但在其他情况下计算结果与真实值误差很大；反射系数法通过地面的电导率σ、相对介电常数ε_r以及入射波的极角θ分别求出地面的水平反射系数和垂直反射系数，从而准确估算出来波方向，但由于该方法需要预先知道地面参数，故其应用场景受到了一定的限制；阵列抑制算法巧妙地利用地面反射波和直达波在相位延迟和入射角方面的关系，通过移相操作，生成抑制反射波的新数据，再对其进行处理，准确计算出DOA.通过比较分析可以得出，阵列抑制算法可用于任何类型的实际地面，且无需知道实际地面参数，同时该算法具有很好的准确性，因此其应用场景不受限制，具有很好的理论研究和实际应用价值.     

Adaptable,Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA

This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core.     

Analysis of the convergence behavior of adaptivedistributed-arithmetic echo cancellers

Adaptive distributed-arithmetic echo cancellers are well suited for full-duplex high-speed data transmission. They allow a simpler implementation than adaptive linear transversal filters, since multiplications are replaced by table look-up and shift-and-add operations. Various tradeoffs between the number of operations and the number of memory locations of the look-up tables can be achieved by segmenting the echo canceller delay line into sections of shorter length. Adaptivity is achieved by a decision-directed stochastic gradient algorithm to adjust the contents of the look-up tables. The author adopts the mean-square error criterion to investigate the convergence behavior of adaptive distributed-arithmetic echo cancellers. Under the assumption that the look-up values are statistically independent of the symbols stored in the echo canceller delay line, he obtains an analytical expression for the mean-square error as a function of time. The maximum speed of convergence and the corresponding optimum adaptation gain are also determined. Simulation results for a full-duplex quaternary partial response class-IV system are presented and compared with theoretical results     

Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures

Emerging wireless applications consistently demand higher data rates. Unfortunately, it is challenging to achieve high data rates within the limited amount of available frequency spectrum. Hence, enhanced spectral efficiency and link reliability within the available frequency spectrum are of the utmost importance in current and next generation wireless protocols. To attain high spectral efficiency and link reliability, wireless protocols employ increasingly complex 2-dimensional techniques that involve computationally-intensive matrix operations. Multiple-Input Multiple-Output (MIMO) communication is an example of a promising technique employed by wireless protocols to deliver higher data rates at the cost of increased algorithmic complexity. Application Specific Integrated Circuits (ASICs) have traditionally been used to implement compute-intensive wireless protocols. The wireless industry has been gradually moving towards an alternative programmable platform called Software Defined Radio (SDR) due to its significant benefits, such as reduced development costs, and accelerated time-to-market. The computationally-intensive matrix operations used in current and next generation wireless protocols are extremely expensive to implement in SDR platforms with conventional Digital Signal Processor (DSP) instruction sets. Hence there is a need for novel instructions, hardware designs and algorithm enhancements to enable higher spectral efficiency on SDR platforms. In this paper, we propose Single Instruction Multiple Data (SIMD) CoOrdinate Rotation DIgital Computer (CORDIC) instruction set extensions with CORDIC hardware support to speedup computationally-intensive matrix decomposition algorithms. The CORDIC instruction set extensions have been implemented on the Sandbridge Sandblaster SB3000 SDR platform and evaluated on conventional algorithms used for decomposing a closed loop 4-by-4 Worldwide Interoperability for Microwave Access (WiMAX) MIMO channel into independent Single-Input Single-Output (SISO) channels. Our experimental results on the closed-loop MIMO channel decomposition using CORDIC instructions demonstrate more than 6x speedup over a Sandblaster baseline implementation that uses state-of-the-art SIMD DSP instructions. The CORDIC instructions also provide similar numerical accuracy when compared to the baseline implementation. The techniques we propose in this paper are also applicable to other SDR and embedded processor architectures.     

用采样数据进行网络函数有理逼近的一种有效方法

随着集成电路工作频率达到GHz范围和电路朝更大更密集型发展的趋势,互连与封装等寄生效应对电路的影响越来越大,如何准确地对这些效应进行分析模拟,成为当前集成电路CAD中十分重要的任务。在高频率时,互连与封装的特性只能通过测量或电磁场的数值模拟给出的一组不同频率上网络函数的采样值描述。基于这些采样值通过有理插值构造网络函数的近似宏模型是实现这类电路模拟的关键,但这一问题在数值上是高度病态的。本文通过复频率的双线性变换提出了获得稳定有理逼近的一个新方法,可有效克服这一困难。文中给出的例子实现了高达60阶的有理插值。     

Parameter estimation with multiple sources and levels ofuncertainties

Least-squares designs are sensitive to errors in the data, which can be due to several factors including the approximation of complex models by simpler ones, the presence of unavoidable experimental errors when collecting data, or even due to unknown or unmodeled effects. We formulate a new design criterion that treats multiple sources of uncertainties in the data with possibly varied degrees of intensity. We show that the solution has a regularized form, with one regularization parameter for each source of uncertainty. The parameters turn out to be model dependent and can be determined optimally as the nonnegative roots of certain coupled equations. Applications in array signal processing and image processing are considered     

流水线CORDIC算法的FPGA实现

坐标旋转计算机（CORDIC）算法可以将多种难以用硬件电路直接实现的复杂运算分解为统一的简单移位、加法运算,然后逐次逼近结果。这种方法很好地兼顾了精度、速度和硬件复杂度,因而在数字信号处理领域得到了广泛应用。首先简要介绍了CORDIC算法的原理,然后基于现场可编程门阵列（FPGA）实现了流水线结构的CORDIC算法,仿真结果表明,其输出误差很小,与理论值基本一致。     

High-Speed CORDIC Based on an Overlapped Architecture and a Novel σ-Prediction Method

This paper presents architectural and algorithmic approaches for achieving high-speed CORDIC processing in both of the two operating modes: vectoring and rotation. For vectoring mode CORDIC processing, a modified architecture is proposed, which aims at reduction of computation time by overlapping the stages for redundant addition and selection of rotation direction. In addition, a novel rotation direction prediction scheme for rotation mode CORDIC is presented. The method is based on approximation of the binary angle input to a number with the arctangent weights (tan^–1 2^–i). The implementation is designed to keep the fast timing characteristics of redundant arithmetic in the x/y path of the CORDIC processing. The characteristics are analyzed with respect to latency time and area, and compared with those obtained by conventional CORDIC implementations. The results show that the proposed techniques reduce not only the block latency but also the overall computation time. Thus, they achieve higher throughput in pipelining.     

A CORDIC processor for FFT computation and its implementation usinggallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 μm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 μs, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors     

Numerical Accuracy of Fast Fourier Transforms with CORDIC Arithmetic

The vector rotation operation in the butterfly of a Fast Fourier Transform (FFT) can be calculated by a complex multiplier as well as a CORDIC (COordinate Rotation DIgital Computer). For these vector rotation blocks, expressions for the maximum numerical error are derived. It is shown that the error introduced by the CORDIC can be reduced by increasing the size of the input vector of the CORDIC and decreasing the size of the output vector by the same amount. This input vector scaling makes the reduction possible of the number of bits in the data path of the CORDIC. The impact on the Signal to Noise Ratio (SNR) of the FFT is evaluated when a CORDIC is applied in the FFT butterfly.