一种适用于便携式多模式全球卫星导航系统接收机的低功耗宽带频率合成器设计

本文提出了一种适用于便携式多模式全球卫星导航系统（GNSS）接收机的低功耗宽带频率合成器,并分析了GNSS接收机频率合成器的设计要点。该频率合成器通过采用具有调谐曲线补偿功能的单一VCO实现了较宽的频率范围,同时具有较低的功耗和好的相位噪声性能。该频率合成器在CMOS 0.18um 1P6M工艺上流片验证成功。测试表明,带内相位噪声小于-95dBc@200KHz,频率调谐范围为1.47-1.83GHz,而整个电路面积仅为0.55mm2,整个频率合成器功耗小于11.2mw。     

Digital Coarse Tuning Loop for Wide-Band Fast-Settling Dual-Loop Frequency Synthesizers

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

快速锁定、宽带双环路频率综合器的数字粗调环路

提出了一种用于宽带、双环路频率综合器的粗调环路结构.该粗调环路由数字电路设计实现,包含逐次逼近寄存器和新结构的频率比较单元两个模块.其中,频率比较单元在一定的参考时间内对预分频器的输出信号周期进行计数,然后通过比较计数结果与预设值的大小来估计VCO输出频率.对比较误差进行了详细分析,分析表明,在一定的比较时间内该结构的比较误差比现有结构小20倍,而且由于重复利用可编程分频器作为粗调环路的一部分,整体电路也大为简化.     

一种实现自调谐频率综合器的算法和结构

在集成的频率综合器中 ,工艺、温度和电源电压的变化使得频率综合器产生的中心频率和频率调谐范围与期望值发生偏移。文中指出了一种自调谐频率综合器的算法和结构 ,利用特殊结构的可编程压控振荡器和自调谐算法实现宽调谐范围的频率综合器 ,进而充分涵盖期望的输出频段。用 0 2 5 μmCMOS工艺设计了一个中心频率 2 2GHz,调谐范围为 338MHz的频率综合器 ,用于IEEE80 2 11b/g无线局域网系统的超外差收发机中 ,可以充分满足标准要求的 80MHz的调谐范围 ;给出了锁定某一目标频率时自调谐算法的具体工作过程 ,结果表明该算法和结构是正确的。     

UHF宽带数字频率合成器的设计

频率合成器在现代电子系统中应用日益广泛,UHF（超高频）宽带数字频率合成器是地囿数字电视广播覆盖网的重要设备——数字电视激励器和转发器中的主要组成单元。提出了一种UHF宽带小频率步进、低相噪数字频率合成器的设计方法,介绍了系统各部分的设计方法、器件选择、相关参数的计算及PCB（印制电路板）设计,最后给出了系统射频输出信号相噪测试结果,验证了本设计方法的有效性和设计方案的可行性。     

一种适用于2.4GHz ISM射频波段的全集成CMOS压控振荡器

提出了一种频率可调范围约 2 30MHz的全集成LC压控振荡器 (VCO) .该压控振荡器是用 6层金属、0 18μm的标准CMOS工艺制造完成 .采用MOS晶体管和电容组合来实现等效变容管 ,为降低芯片面积仅使用一个片上螺旋电感 ,并实施了低电压、低功耗的措施 .测试结果表明 ,该压控振荡器在电源电压为 1 8V的情况下功耗约为10mW ,在振荡器中心频率为 2 46GHz时的单边带相位噪声为 - 10 5 89dBc/Hz @6 0 0kHz .该压控振荡器可以应用于锁相环电路或频率综合器中.     

锁相环CD4046的应用设计及研究

讨论锁相环的原理及应用,设计基于锁相环CD4046的锁相频率合成器和鉴频电路,对电路作了实验验证和分析。该设计电路简单实用。能较好地说明锁相环的应用设计过程及优势,利于对锁相环应用的研究。     

A fast AFC technique with self-calibration for fast-locking PLLs

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value from MIN, MAX and the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18?µm CMOS process. The AFC time decreased from 40 to 0.4?µs employing the proposed scheme such that the total lock time is 40?µs with the loop bandwidth of 40?kHz.     

频率范围2.95-3.65GHz采用调谐曲线补偿的CMOS LC-VCO

本文提出了利用一种新型的谐振回路对调谐曲线进行补偿,频率范围为2.95~3.65GHz的CMOS LC-VCO. 该VCO采用AMOS可变电容,能实现其Q值和调谐范围的同时优化,通过线性化调谐曲线,减少了AM-PM噪声的转换。电路通过 0.18μm 1P6M CMOS工艺验证,面积仅为0.24mm2,整个VCO含输出缓冲在内的功耗为5.04mW,相位噪声在100KHz偏移处是-91dBc/Hz。     

A novel 2.95–3.65 GHz CMOS LC-VCO using tuning curve compensation

This paper presents a new CMOS LC-VCO with a 2.95–3.65 GHz tuning range.The large tuning range is achieved by tuning curve compensation using a novel varactor configuration,which is mainly composed of four accumulation-mode MOS varactors（A-MOS）and two bias voltages.The proposed varactor has the advantages of optimizing quality factor and tuning range simultaneously,linearizing the effective capacitance and thus greatly reducing the amplitude-to-phase modulation（AM-PM）conversion.The circuit is validated by simulations and fabricated in a standard 0.18μm 1P6M CMOS process.Measured phase noise is lower than–91 dBc at 100 kHz offset from a 3.15 GHz carrier while measured tuning range is 21.5%as the control voltage varies from 0 to 1.8 V.The VCO including buffers consumes 2.8 mA current from a 1.8 V supply.     

一种集成新型相位切换预分频器和高品质因素压控振荡器5 GHz CMOS频率综合器

本文实现了一种集成新型相位切换预分频器和高品质因素压控振荡器的锁相环频率综合器。该频率综合器在考虑噪声性能的基础上进行系统参数设计。预分频器采用了一种不易受工艺偏差影响的相位切换方式。对压控振荡器的电感开关电容和压控电容的品质因素进行了优化。与其他文献相比,该频率综合器使用相近的功耗取得更好的噪声性能。本文提出的频率综合器采用SMIC0.13微米工艺流片,芯片面积为11502500 μm²。当锁定在5 GHz时,其功耗在1.2V电源电压供电时为15mA。此时,1MHz频偏处相位噪声为-122.45dBc/Hz。     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.     

A 2 GHz Phase-Locked Loop Frequency Synthesizer with On-Chip VCO

This paper discusses the implementation of the building blocks for a 2 GHz phase-locked loop frequency synthesizer in a standard 0.5 m BiCMOS process. These blocks include a low-power optimized dual modulus prescaler which is able to operate with input frequencies up to 2.7 GHz, a phase detector with extremely constant gain throughout the input phase difference range, a chargepump with a rail-to-rail output, and an on-chip voltage-controlled oscillator.     

适用于高速Δ-Σ模数转换器的功耗可配置锁相环频率综合器

本文提出了一个适用于Δ-Σ模数转换器的基于锁相环结构的频率综合器,该频率综合器使用65纳米CMOS工艺实现,频率范围为35-130和300-360兆赫兹。文中提出的频率综合器能够工作在低相位噪声模式和低功耗模式,从而满足系统要求。为了实现这两个模式的切换,片上集成了一个连接4分频器的高频LC压控振荡器和一个连接2分频器的环形压控振荡器。测试结果表明,在1.2伏电源电压下,该频率综合器在低相位噪声模式下消耗1.74毫瓦功耗,1兆频偏处的相位噪声为-132dBc/Hz,标准差周期抖动为1.12皮秒;在低功耗模式下消耗0.92毫瓦功耗,1兆频偏处的相位噪声为-112dBc/Hz,标准差周期抖动为7.23皮秒。     

Bottom-series coupled quadrature VCO using the inductive gate voltage boosting technique

This article presents a new low-voltage bottom-series coupled quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled VCOs with the bottom-series coupling transistors. The low-voltage operation is obtained via an inductive gate voltage boosting technique. The proposed CMOS QVCO has been implemented with the TSMC 0.18?µm CMOS technology and the die area is 0.897?×?0.767?mm². At the supply voltage of 0.7?V, the total power consumption is 1.5?mW. The free-running frequency of the QVCO is tuneable from 3.77 to 4.12?GHz as the tuning voltage is varied from 0.0 to 0.7?V. The measured phase noise at 1?MHz frequency offset is ?123.35?dBc/Hz at the oscillation frequency of 4.12?GHz and the figure of merit of the proposed QVCO is ?193.5?dBc/Hz.     

1．3～2．2 GHz低噪声低功耗 CMOS LC VCO的设计

基于TSMC 0．18μm RFCMOS工艺,设计并实现了一个宽带低功耗低相位噪声的高性能压控振荡器（VCO）．为实现1．3～2．2 GHz调谐范围,VCO采用7‐bit（128根调谐曲线）固定电容阵列,同时也获得了超低的增益,降低了相位噪声．为弱化宽调谐范围带来的增益波动,VCO采用3‐bit可变电容阵列来提升低带曲线的斜率,以期与高带一致．为实现每根曲线的宽线性范围,可变电容采用分布式偏置电压技术．为降低相位噪声,还提出了一种输出零偏置架构以及电流源噪声滤除技术．测试结果表明,调谐电压的线性范围为0．2～1．6 V ;VCO输出频率范围为1．3～2．17 GHz ;高带调谐曲线叠合超过50％,低带超过80％;VCO增益仅为19 M Hz／V ;增益波动范围为13～25 M Hz／V ．当振荡频率为1312 M Hz ,1 M Hz 频偏处相位噪声为－116．53 dBc／Hz ;当振荡频率为2152 M Hz ,1 M Hz频偏处相噪为－112．78 dBc／Hz ．VCO功耗电流为1．2～3．2 mA ,电源电压为1．8 V ．提出的VCO既能提供51％的频率覆盖,又能实现低相位噪声,已经被成功应用于工业自动化无线传感网（WIA ）射频收发机芯片中．     

一种提供5位频带切换控制的5GHz压控振荡器

设计了一种提供5位频带切换控制的5GHz电容电感压控振荡器,采用NMOS-PMOS交叉耦合结构,并且为消除电流源的闪烁噪声而应用电阻偏置调节工作电流.电路采用TSMC RF0.18μm CMOS工艺进行仿真,仿真结果显示,在1.8V电源电压下,在偏离中心频率1MHz处的相位噪声为-120.8dBc/Hz,调谐范围为24.6%,功耗仅为2.3mW.