一种适用于便携式多模式全球卫星导航系统接收机的低功耗宽带频率合成器设计

本文提出了一种适用于便携式多模式全球卫星导航系统（GNSS）接收机的低功耗宽带频率合成器,并分析了GNSS接收机频率合成器的设计要点。该频率合成器通过采用具有调谐曲线补偿功能的单一VCO实现了较宽的频率范围,同时具有较低的功耗和好的相位噪声性能。该频率合成器在CMOS 0.18um 1P6M工艺上流片验证成功。测试表明,带内相位噪声小于-95dBc@200KHz,频率调谐范围为1.47-1.83GHz,而整个电路面积仅为0.55mm2,整个频率合成器功耗小于11.2mw。     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18μm CMOS technology.A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance.A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature(I/Q) local oscillating signal.A high-speed 8/9 dual-modulus prescaler(DMP),a programmable-delay phase frequency detector without dead-zone problem,and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz,and the phase noise is-98.53 dBc/Hz at 100-kHz offset and -121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply.The total area of the receiver is 2.4×1.6 mm~2.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...     

一种低功耗频率预置快速锁定的锁相环频率综合器

本文提出了一种2.4GHz低功耗频率预置快速锁定的锁相环频率综合器,该频率综合器使用0.18um 的CMOS 工艺制作。设计了低功耗的混合信号压控振荡器,双模预置分频器,数字处理器和非易失性存储器来降低整体系统的功耗和减小锁定时间。数字处理器可以在工艺偏差的情况下自动的校正压控振荡器的预置频率,使得对振荡器频率的预置可以达到很高的精度。测试结果表明,在1.8V 的电源电压下,频率综合器的电流消耗为4mA,它的典型的锁定时间小于3us。     

A 5 GHz CMOS frequency synthesizer with novel phase-switching prescaler and high-Q LC-VCO

A phase-locked loop(PLL) frequency synthesizer with a novel phase-switching prescaler and a high-Q LC voltage controlled oscillator(VCO) is presented.The phase-switching prescaler with a novel modulus control mechanism is much more robust on process variations.The Q factor of the inductor,I-MOS capacitors and varactors in the VCO are optimized.The proposed frequency synthesizer was fabricated by SMIC 0.13μm 1P8M MMRF CMOS technology with a chip area of 1150×2500μm~2.When locking at 5 GHz,the current consumption is 15 mA from a supply voltage of 1.2 V and the measured phase noise at a 1 MHz offset is -122.45 dBc/Hz.     

一种应用于GPS接收机的低功耗CMOS频率合成器

提出了一种应用于GPS/Galileo L1/E1波段接收机的低功耗频率合成器,并成功在0.18 µm CMOS 工艺中实现。通过在锁存器的输出端引入时钟控制管,高速源耦合逻辑预分频器相比传统结构,最高分频频率得到提高。测试结果显示,该频率合成器在1.8V的电源供电情况下消耗电流6 mA,带内相噪小于-87 dBc/Hz(15 KHz频率偏移处),杂散小于-65 dBc,核心电路面积0.6 mm2。     

A low-power CMOS frequency synthesizer for GPS receivers

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscil-lator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of-87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm2.     

一种适用于多带OFDM超宽带系统中的快速跳频3子带CMOS频率综合器

A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.     

一种应用于GNSS接收机常数环路带宽的小数频率合成器

提出了一种应用于手持式民用GNSS接收机常数环路带宽的小数频率合成器,并在0.13μm 1P6M 的CMOS工艺中实现。通过离散的工作区域,LC-VCO用简单的结构获得宽的调节范围和小的压控灵敏度。提出的杂散抑制技术来最小化由于鉴频鉴相器和电荷泵引入的相位偏移。当PLL输出频率改变或温度变化时,通过自动环路校正模块自适应调整电荷泵电流保持优化的环路带宽不变。测试结果显示,该频率合成器带内相位噪声小于-93dBc（10 kHz 频率偏移处）,杂散小于-70 dBc, 环路带宽变化小于?3%;在1V的电源供电下,整个合成器（不包括本振测试buffer）消耗4.5mA电流,面积为0.5mm2。     

A fast-hopping 3-band CMOS frequency synthesizer for MB-OFDM UWB system

ment shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 × 1.8 mm2.     

一种集成新型相位切换预分频器和高品质因素压控振荡器5 GHz CMOS频率综合器

本文实现了一种集成新型相位切换预分频器和高品质因素压控振荡器的锁相环频率综合器。该频率综合器在考虑噪声性能的基础上进行系统参数设计。预分频器采用了一种不易受工艺偏差影响的相位切换方式。对压控振荡器的电感开关电容和压控电容的品质因素进行了优化。与其他文献相比,该频率综合器使用相近的功耗取得更好的噪声性能。本文提出的频率综合器采用SMIC0.13微米工艺流片,芯片面积为11502500 μm²。当锁定在5 GHz时,其功耗在1.2V电源电压供电时为15mA。此时,1MHz频偏处相位噪声为-122.45dBc/Hz。     

一个含宽带VCO 和多模正交分频器的可输出220MHz-1100MHz 频率的低噪声频率综合器

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase(I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation(WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator(VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 d Bc/Hz at a 10 k Hz offset and 131 d Bc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 m CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.     

适用于超宽带系统的低功耗CMOS频率合成器研究

针对脉冲无线电超宽频(IR-UWB)接收系统,提出了一种低功耗频率合成器设计。合成器的设计以一个整数N分频II型四阶锁相环结构为基础,包括一个调谐范围为31%的7位压控振荡器,一组基于单相时钟逻辑的高速分频器。分频器能够合成八个由IEEE标准802.15.4a定义的频率。该集成频率合成器运用65 nm CMOS技术制造而成,面积为0.33 mm2,工作频率范围为7.5–10.6 GHz。测试结果显示,在1.2 V供电下,该合成器的3-dB闭环带宽为100 kHz,稳定时间为15 。测量相位噪声低于-103 dBc/Hz@1MHz,抵消频率为1 MHz。杂散信号功率低于低于-58 dBc。相比其他先进的合成器,提出合成器的工作电流为5.13 mA,功耗仅为6.23mW。     

一种低功耗32nm CMOS分数-N频率合成器设计

为了减少频率合成器的工作能耗,提出了一种新型低功耗的分数-N频率合成器。该合成器消除了电源电压、工艺偏差和温度变化（PVT）对电容的影响,能够产生中等精度时钟脉冲震荡且具有较低的芯片面积。该合成器通过采用频率-电流转换电路,将电路的输出频率与电容比成正比。采用32nm CMOS工艺对提出电路进行了制作。测试结果显示,相比其它类似合成器,提出合成器的功耗和面积更低,总面积仅仅为0.0065mm2,在0.9 V电源电压条件下,功率仅损耗为108 μW。使用4 MHz参考时钟时,输出频率范围为18–156 MHz,频率分辨率为0.8MHz。     

一款应用于无线通信的0.8~4.2 GHz单芯片全数字锁相环频率综合器

本文采用130nmCMOS工艺成功实现了应用于无线通信的0.8 - 4.2 GHz单片全数字锁相环频率合成器。文章提出了一系列的新方法,即采用了高频率分辨率的双带DCO以覆盖系统所需的2.5 GHz至5 GHz带宽;一个溢出计数器可以防止“pulse-swallowing”现象,显著减少了环路锁定时间;提出的NTW-clamp数字模块可以有效防止循环控制字的溢出;修改后的可编程分频器避免了传统架构中失败的边界操作。测量结果表明,该频率合成器的输出频率范围是0.8-4.2 GHz,锁定时间在2.68GHz减少了84%,最好的带内和带外相位噪声性能已达到-100 dBc/Hz,和-125 dBc/Hz,最低参考杂散达到-58dBc。     

一种应用于GNSS/蜂窝网混合定位接收机的多标准频率合成器

A fully integrated hybrid integer/fractional frequency synthesizer is presented.With a single multiband voltage-controlled-oscillator(VCO),the frequency synthesizer can support GPS,Galileo,Compass and TDSCDMA standards.Design is carefully performed to trade off power,die area and phase noise performance.By reconfiguring between the integer mode and fractional mode,different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously.Moreover,a long sequence length,reduced hardware complexity multi-stage-noise-shaping(MASH).-.modulator is employed to reduce fractional spur in the fractional mode.Fabricated in a 0.18 m CMOS technology,the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4-16.2 mA from a 1.8 V power supply.The measured phase noise is lower than-80 dBc/Hz at 100 kHz offset and-113 to-124 dBc/Hz at 1 MHz offset respectively,while the measured reference spur is-71 dBc in integer mode and the fractional spur is-65 dBc in fractional mode.     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。     

An ultra-low power integer-N frequency synthesizer for MICS transceivers

The ultra-low power frequency synthesizer for the transceivers used in the application of Medical Implantable Communication Services (MICS) is presented. The MICS band is from 402 to 405 MHz. Each channel spacing is 300 kHz. Integer-N architecture is used to implement the frequency synthesizer. The post layout simulations show that the total power consumption of the system is less than at 1.2 V power supply. The gains of the charge pump and voltage controlled oscillator (VCO) are and 50 MHz/V, respectively. The standard 300 kHz external clock is used as the reference. The design is carried out in the IBM 90 nm 9LPRF CMOS technology.