A 1.4-V 25-mW 600-MS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 600-MSample/s 6-bit folding and interpolating analog-to-digital converter(ADC) is presented.This ADC with single track-and-hold(T/H) circuits is based on cascaded folding amplifiers and input-connection-improved active interpolating amplifiers.The prototype ADC achieves 5.55 bits of the effective number of bits(ENOB) and 47.84 dB of the spurious free dynamic range(SFDR) at 10-MHz input and 4.3 bit of ENOB and 35.65 dB of SFDR at 200-MHz input with a 500 MS/s sampling rate;it achieves 5.48 bit of ENOB a...     

A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-μm CMOS process and occupies a core area of 0.45 mm².     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-μm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter(ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages. The ADC is realized in the 0.13-μm 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range,poor analog characteristic device...     

A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology

This paper presents a 10-bit 2.5-MS/s successive-approximation-register (SAR) analog- to-digital-converter (ADC) design for micro controller unit of signal process system. Because of the proposed new segmented architecture of 7 MSBs-plus-3 LSBs capacitor–resistor hybrid digital-to-analog-converter using a thermometer decoder for the most significant 5 MSBs, this design achieves superior static nonlinearity and dynamic performance of SNDR, SFDR. Utilizing the proposed deviation calibration technique, the discharging and charging via substrate resulting from deviation of the comparator’s common-mode voltage is cancelled. The ADC is fabricated in a standard 1P5M 0.13-μm CMOS technology. The peak DNL and INL are +0.18/?0.20-LSB, +0.30/?0.25 LSB respectively while the ENOB is 9.52-bit around all process–voltage–temperature corner analysis. At a 2.3-V supply voltage and a 2.5-MS/s sampling rate, the ADC achieves a SNDR of 60.46 dB, SFDR of 75.32 dB while the power dissipation is 0.191-mW, that resulting in a figure of merit of 98.45 fJ/c-s. The die of ADC measures 0.51 × 0.20 mm² resulting in area efficiency of 122.6 μm²/code and compared with the benchmark SAR ADCs, this work is the most area efficient design.     

A 30-mW 8-b 125-MS/s pipelined ADC in 0.13-μm CMOS

An 8-b pipelined ADC constructed in 0.13-μm CMOS is described. This ADC uses a dual-supply technique to yield 8-b performance at a sampling rate of 125 MS/s while consuming 30 mW from 1.8-V and 1.2-V supplies. Active area is 0.4 mm². Numerous challenges associated with this choice of process technology were overcome, such as limited dynamic range, copper metallization and the effects of gate oxide leakage.     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-µm CMOS

A 12-bit 250 MS/s pipeline ADC is presented and implemented in 0.13 µm CMOS process. To reduce the load capacitance of each pipeline stage and save area, the inter-metal capacitors are adopted as input sampling capacitors of the comparators. A fully integrated reference buffer associated with a simulation scheme is proposed to improve the settling speed and PSRR of the differential reference voltage. To reduce the overall power a low cost foreground calibration for capacitor mismatches is employed. The single-stage telescopic with gain-boosting amplifiers and an improved bias is applied in each stage due to its high power efficiency. Additionally, the timing in the sampling phase is optimised to achieve high sampling linearity. Even harmonics induced by parasitic capacitance are analysed profoundly and mitigated at the level of layout. The measured SNDR and SFDR are 63 and 78 dB with 38.1 MHz input, respectively, and remain 63 and 77 dB with Nyquist input. The ADC core area is 1.6 mm² and consumes 165 mW (reference buffer included, LVDS excluded) at 250 MS/s under 1.3 V.     

A 1.1-mW 10-bit 50-MSample/s hybrid two-step ADC in 0.13-µm CMOS technology

This paper presents a hybrid two-step analog-to-digital converter (ADC) that employs a successive approximation register (SAR) ADC and a time-to-digital converter (TDC)-based ADC as coarse and fine converters, respectively. By exploiting the respective advantages of the SAR and TDC architectures, the two-step ADC is realized without a high-gain amplifier for high linearity of a multiplying digital-to-analog converter. Thus, the proposed architecture can implement a low-power ADC without compromising operational speed. In addition, two digital error corrections are used to compensate for TDC error and the final ADC output, respectively. A 10-bit 50 MS/s ADC is fabricated in a 0.13-μm complementary metal–oxide–semiconductor process and occupies a 0.12-mm² die area. Furthermore, it consumes only 1.1 mW and achieves a signal-to-noise distortion ratio and spurious-free dynamic range of 53.67 and 60 dB, respectively, resulting in a 53.7 fJ/conversion-step at a 25-MHz full-scale input.     

A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS

This paper presents a 6-bit low power low supply voltage time-domain comparator. The conventional voltage comparison is moved to time-domain so as to remove pre-amplifier and latch, which enables its feasibility to low supply voltage. The voltage-to-time converter is realized by the proposed linear pulse-width-modulation. The set-up time of the D flip-flop determines the sampling rate of the converter. The resistive averaging relaxes the matching requirement of the parallel comparison cells. The total input capacitance is decreased to less than 40fF in this architecture. The above digital-intensive setting makes the analog-to-digital converter (ADC) benefit from technology scaling in both power consumption and sampling rate. The prototype ADC is fabricated in SMIC 0.18 μm CMOS process. At 40 MS/s and 1.0-V supply, it consumes 540 μW and achieves an effective-number-of-bit of 5.43, resulting in a figure-of-merit of 0.31 pJ/conversion-step and active area of 0.1 mm².     

A 1-V, 82-dB, 2.5-MS/s,single loop,single bit delta-sigma modulator in 0.13-μm CMOS technology

It is challenging to design high speed Delta-Sigma modulator using sub-micron process with low supply voltage. Compared with multi-stage or multi-bit design, the single loop, single bit Delta-Sigma modulator has relaxed requirement for the building blocks under low-voltage operation, which make it possible to get high conversion rate by increasing sampling frequency. In this study, a low voltage, high speed 4th-order Delta-Sigma modulator using input feed-forward is presented. Implemented with 0.13-μm CMOS technology and 1.0-V supply voltage, the discrete-time Delta-Sigma modulator achieves 2.5-MS/s conversion rate and 82-dB dynamic range, with the sampling frequency of 160-MHz and OSR of 64.     

A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.     

An 8-bit 1 GS/s folding and interpolating ADC with a base-4 architecture

A base-4 architecture for folding and interpolating ADC is proposed. It employs cascaded folding and interpolating topology with both the folding factors and interpolating factors of 4. Duo to that the base-4 folding and interpolating has an intrinsic relationship with the quantization process which is base-2, the architecture requires only 2 × N + 6 comparators for an N-bit ADC. What’s more, the coarse flash ADC can be eliminated because all the most significant bits can be conveniently extracted from the intermediate signals as the “byproduct” of the folding amplifiers. In addition, the base-4 architecture can be extended to higher resolution easily because of the modularized and unified configuration. This architecture is implemented with a 1 GS/s 8-bit ADC in 0.35 μm SiGe BiCMOS process. Measurement results reveal the chip exhibits DNL of 0.30/?0.26 LSB and INL of 0.80/?0.80 LSB. The ENOB is 6.9 LSB at 10.1 MHz input. The SNDR is above 42 dB over the first and the second Nyquist zone. The SFDR is above 45 dB over the first Nyquist zone and the second Nyquist zone. The ERBW is over 1.2 GHz.     

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm².     

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented.The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter,which are based on well-designed calibration reference, calibration DAC and comparators.The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.     

A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology

A novel low-voltage rail-to-rail parallel time-based analog-to-digital converter (ADC) is proposed. The proposed ADC works like a conventional flash ADC except that the process is performed in the time-domain. Since the operation of analog integrated circuits at low supply voltages is limited, converting the voltage signals to the time domain improves the efficiency of the circuit. In this paper, a constant-delay ladder is utilized to make the reference delay-times to compare with the input signal. A 1-V 5-bit 500 MS/s ADC has been designed and simulated in 0.18 µm CMOS technology consumed 3.66 mW. The simulation results show 0.3lsb and 0.2lsb for INL and DNL respectively. Signal-to-noise and distortion ratio (SNDR) of the proposed ADC is 26.7 dB at Nyquist frequency. The rail-to-rail operation and linearity of the voltage-to-time converter (VTC) improved the efficiency of the ADC comparing to the similar time-based ADCs. The figure-of-merit (FoM) of the ADC is about 0.31 (pJ/conv.step).

     

Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q~2 random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS samplin...