一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.     

一款新型电荷泵功率管驱动电路

提出了一款新型功率管驱动电路。P沟道功率管驱动电路加入了防死锁模块防止了死锁的出现,提高了瞬态响应;N沟道功率管驱动电路加入了附加的充电支路,提高了驱动能力和瞬态响应。整个电路基于0.6μm BCD工艺,在Cadence Spectre下仿真。和传统的功率管驱动电路相比,新的P沟道功率管驱动电路的上升时间由60ns减少到14ns,下降时间由240ns减少到30ns,并且功耗从2mW减少到1mW;新的N沟道功率管驱动电路的上升时间由360ns减少到27ns,功耗从1.1mW减少到0.8mW。     

适用于EEPROM的低功耗高效率的高压产生电路

本文提出了一种应用于嵌入式EEPROM的低功耗和高效率的高电产生电路。低功耗的实现是基于电容分压电路和控制时钟的稳压电路技术;高效率是由于采用了零阈值Vth MOSFET和电荷传输开关技术的电荷泵。该高电压电路采用0.35 μm CMOS工艺流片。测试结果表明,高电产生电路的功耗约150.48 μW和电荷泵效率高达83.3％,因此高电产生电路也可广泛用于低功耗Flash中。     

一种高效的大功率宽带整流电路

提出了一种由π型匹配枝节、整流二极管、直通滤波器组成的高效大功率宽带整流电路。采用2只HSMS-282P肖特基二极管桥设计单级倍压整流电路,使电路在整流效率不下降的情况下提升输入的功率容量;采用π型匹配枝节实现阻抗匹配,使电路具有宽频特性,同时其并联短路枝节可以作为输入滤波器,实现小型化和整流效率的提高。直通滤波器用于抑制基频和二极管非线性产生的高次谐波,以提高整流效率。实测结果表示：在2.05~2.6 GHz带宽内整流效率大于60%;在2.45 GHz工作频率和35 dBm输入功率下,整流电路在330 Ω负载上获得70%的整流效率。该整流电路具有整流效率高、功率容量大、频带宽的特性,可为工程人员设计大功率微波整流电路提供设计指导。     

用于TFT-LCD驱动芯片的省面积高效率内置电荷泵

An area-saving and high power efficiency charge pump is proposed, and methods for optimizing the operation frequency and improving the power efficiency are discussed. Through sharing coupling capacitors the proposed charge pump realizes two DC-DC functions in one circuit, which can generate both positive and negative high voltages. Due to sharing of the coupling capacitors, as compared with a previous charge pump designed by us for a TFT-LCD driver IC, the die area and the amounts of necessary external capacitors are reduced by 40% and 33%, respectively. Furthermore, the charge pump＇s power efficiency is improved by 8% as a result of employing the new topology. The designed circuit has been successfully applied in a one-chip TFT-LCD driver IC implemented in a 0.18 μm low/mid/high mixed-voltage CMOS process.     

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

in a 0.18μm low/mid/high mixed-voltage CMOS process.     

用于相变存储器的超低输出纹波2X/1.5X电荷泵

本文针对相变存储器编程驱动电路,提出了一种超低输出电压纹波的开关电容型电荷泵。该电荷泵可根据输入电压的不同,自适应工作在2X/1.5X升压模式之间,以获得更高的电源转换效率。相比于传统开关电容型电荷泵,在充电阶段泵电容被充电至预先设定的电压值Vo-VDD(Vo为预期的输出电压);放电阶段,泵电容串联在输入电压VDD与输出端,通过此方法将电荷泵输出端电压稳定在Vo,并有效的降低了由于电荷分享所造成的输出纹波。在中芯国际40nm标准CMOS工艺模型下,对电路进行了仿真验证,结果表明在输入电压为1.6-2.1V,输出2.5V电压,最大负载电流为10mA,输出电压纹波低于4mV,电源效率最高可达91%。     

A multi-mode low ripple charge pump with active regulation

In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented.The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.     

采用动态环路调整的多模式低纹波低纹波电荷泵的设计

In order to improve efficiency and reduce the output ripple, a novel multi-mode charge pump is presented. The proposed charge pump includes dual-loop regulation topology-skip and linear modes. It consumes low quiescent current in skip mode for light loads, and produces low ripple in linear mode for heavy loads, which closes the gap between linear mode and skip mode with active regulation; a multi-mode charge pump employing the technique has been implemented in the UMC 0.6-μm-BCD process. The results indicate that the charge pump works well and effectively; it has low ripple with special regulation, and minimizes the size of the capacitance, then decreases the area of the PCB board. The adjustable output of the positive charge pump is 10-30 V, and the maximum output ripple is 100 mV when the load current is 200 mA. The line regulation is 0.2%/V, and load regulation is 0.075%.     

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm². Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.     

PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

低频率电荷泵锁相环设计

设计一款音频范围内的电荷泵锁相环,采用动态D触发器鉴频鉴相器及电流舵差分输入电荷泵。压控振荡器采用了对电容充放电的形式产生震荡波形,实现低频输出。采用HHNEC BCD035工艺并用Cadence软件实现仿真,实现250 kHz频率锁定,锁定时间为80μs,锁定时相位差为75 ns且压控振荡器控制电压纹波为5 mV。     

一种采用PVT不敏感电荷传输电路的27mW 10位125MSPS 电荷域流水线模数转换器

A low power 10-bit 125-MSPS charge-domain(CD) pipelined analog-to-digital converter(ADC) based on MOS bucket-brigade devices(BBDs) is presented.A PVT insensitive boosted charge transfer(BCT) that is able to reject the charge error induced by PVT variations is proposed.With the proposed BCT,the common mode charge control circuit can be eliminated in the CD pipelined ADC and the system complexity is reduced remarkably.The prototype ADC based on the proposed BCT is realized in a 0.18μm CMOS process,with power consumption of only 27 mW at 1.8-V supply and active die area of 1.04 mm~2.The prototype ADC achieves a spurious free dynamic range(SFDR) of 67.7 dB,a signal-to-noise ratio(SNDR) of 57.3 dB,and an effective number of bits(ENOB) of 9.0 for a 3.79 MHz input at full sampling rate.The measured differential nonlinearity(DNL) and integral nonlinearity (INL) are +0.5/-0.3 LSB and +0.7/-0.55 LSB,respectively.     

一种带有片上电荷泵自动调谐结构的非对称带通滤波器的设计

摘要：提出了一种采用片上电荷泵自动调谐结构的MOSFET-C非对称带通滤波器的设计方案,并在UMC（联合电子公司）0.18um标准CMOS工艺线上流片得到验证。带有调谐系统的滤波器采用主从技术进行连续调谐,完成调谐功能后电荷泵输出调谐电压为2.663V,远高于电源电压,提高了滤波器的线性度。非对称带通滤波器带宽为（2.73MHz,5.34MHz）且具有3阶低通和2阶高通特性。以50欧姆作为源阻抗,滤波器带内3阶交调量（IIP3）为16.621dBm。输入参考噪声为47.455uVrms。在1.8V电源电压下,主滤波器功耗为3.528mW,自动调谐电路功耗为2.412mW。带有自动调谐系统的滤波器整个系统占芯片面积0.592mm2,可用于无线局域网,全球定位和蓝牙等系统中。     

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.