PMOS-switching dual-path charge pump in standard twin-well CMOS technology

In this article a new charge pump circuit is presented, which is feasible for implementation with the standard twin-well CMOS process. The proposed charge pump employs PMOS-switching dual charge-transfer paths and a simple two-phase clock. Since charge transfer switches are fully turned ON during each half of the clock cycle, they transfer charges completely from the present stage to the next stage without suffering threshold voltage drop. During one clock cycle, the pump transfers charges twice through two pumping paths which are operating alternately. Test chips have been fabricated in a 0.35-μm twin-well CMOS process. The output voltage of a 4-stage charge pump with each pumping capacitor of 7.36 pF measures 6.7 V under a 1.5 V power supply and 20 MHz clock frequency. It can supply a maximum load current of about 180 μA. Although the proposed circuit exhibits somewhat inferior performances against triple-well charge pumps using additional mask and process steps, it shows at least 60% higher voltage gain at V _DD = 0.9 V, approximately 10% higher peak power efficiency at V _DD = 1.5 V, much larger output current drivability and faster initial output rising than traditional twin-well charge pumps. This new pumping efficient circuit is suitable for design applications with a low-cost standard twin-well CMOS process.     

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

采用电荷泵箝位调整器的BUCK型DC-DC驱动电路

为了提高驱动效率,设计了一种新颖的适用于BUCK型DC-DC的驱动电路,在芯片内部采用一个电荷泵和自适应死区时间控制逻辑的驱动电路。当芯片正常工作时,输出级低端LDNMOS管的驱动电平通过较大的电荷泵电容稳定在5.5V左右,输出级高端LDNMOS管的驱动电平通过自举电容高达29.93V,从而实现对DC-DC输出级高端和低端的驱动,这样既提高了驱动效率,又减少了对外部多个电源的需求。采用此电路的一款电流模BUCK型DC-DC已在UMC06μmBCD工艺线投片,芯片效率高达94%,输出级高端和低端LDNMOS的导通电阻为120mΩ,最大输出电流为5A,该驱动电路工作良好,芯片面积减小了15.4%。     

一种PMOS管传输型高效电荷泵电路设计

设计了一种基于传统Dickson结构的PMOS管传输型电荷泵电路。电路通过衬底电位跟随器实现PMOS管传输,避免了传输过程中阈值电压损失;通过电阻分压反馈网络、控制振荡器输出达到稳压的目的;在电荷泵不工作时,各个子电路关断,实现低功耗设计。仿真结果表明,电路效率高,上电时间短,纹波小;采用SMIC 0.18μm工艺流片,电路达到设计要求,输出高压稳定,驱动能力强,在1M EEPROM电路芯片中得到实际应用。     

新型浮栅MOS单管动态比较器设计

提出一种新型浮栅MOS单管动态比较器的电路结构。以浮栅MOS单管为核心,根据浮栅电荷的保持特性,在时钟控制下,两个电压分时地输入浮栅MOS管从而引起浮栅电位变化,相对变化后的浮栅电位决定着比较管的再通断,使预充电的输出电容与源极电容重新分配电荷,通过输出电容上电压是否发生变化来反映比较结果。单管比较避免差分对管由于工艺偏差所引起的输入失调问题,而且以浮栅偏置抵消MOS管的阈值。采用charted0.35μmCMOS工艺设计电路,面积约为0.003mm2,经前、后仿真和流片测试,结果表明,电路功能正确。并且在3.3V电源电压下、比较时间为0.4μs时,平均功耗为2.8mW。     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

双模式高集成负电荷泵电路设计

提出了一种新颖的双模式高集成开关电容电荷泵。该电荷泵集成高频振荡器、电平移位、逻辑驱动以及4个功率MOSFET开关。与传统电荷泵相比,该电路可以工作在单电源以及双电源两种模式。单电源模式下,输出电压为-VCC;双电源模式下,输出电压为-3×VCC。电路采用0.35μm BCD工艺实现。测试结果表明:室温时,单电源模式和双电源模式下电荷泵输出电流分别为36 mA和80 mA时输出电压分别为-3.07 V和-12.10 V。在-55℃到125℃温度范围内,单电源模式和双电源模式下电荷泵输出电流分别为24 mA和50 mA时输出电压分别低于-3.06 V和-12.35 V。该电荷泵在两种模式下工作特性良好,已应用于相关工程项目。     

低电源电压条件下的双阈值电压泵

由于存在逆向电流,利用电流传输开关特性的改进型的电压泵（NCP-1）的电压增益被大大减弱.本论文提供了一个新的方法.通过使用双阈值电压CMOS代替单阈值电压CMOS,不但消除了逆向电流,而且对低电压有很好的放大增益.PSPICE模拟结果,当电源电压为0.5V时,6级电压泵可使输出电压放大到2.68V.     

A technique to increase the efficiency of high-voltage charge pumps

A charge pump that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. A 10% increase of voltage gain has been achieved in the proposed switching technique when compared with a traditional Dickson charge pump. The top plate and bottom plate switching technique have also been illustrated to improve the efficiency of the charge pump. A six-stage Dickson charge pump was designed to produce a 19 V output from a 3.3-V supply, using a 4 MHz, two-phase nonoverlapping clock signal driving the charge pump. The design was fabricated in a 0.35-/spl mu/m SOI CMOS process. An efficiency of 79% is achieved at a load current of approximately 19 /spl mu/A.     

DC-DC电荷泵的研究与设计

以Dickson电荷泵的基本原理为出发点，研究了一种将正电压输入转为负电压输出的开关电容电路。由于开关电容的充放电特点，为确定电容时间常数，采用非交叠时钟控制信号避免了由于时钟交叠而造成的当电容充电还未完成即对下一级电容进行放电的现象。同时，参考功率MOS-FET的电容模型通过增大驱动电路的电流减小了开关管的上升延时，提高了开关动作的速度，使转换效率得到明显提高。此电路结构简单，性能优良，易于集成，可广泛应用于输出负电压的电源产品中。     

A charge pump for driving CMOS active pixel reset

To overcome the limitation of low image signal swing range and long reset time in four Iransistor CMOS active pixel image sensor, a charge pump circuit is presented to improve the pixel reset performance. The charge pump circuit consists of two stage switch capacitor serial voltage doubler. Cross-coupled MOSFET switch structure with well close and open performance is used in the second stage of the charge pump. The pixel reset transistor with gate voltage driven by output of the pump works in linear region, which can accelerate reset process and complete reset is achieved. The simulation results show that output of the charge pump is enhanced from 1.2 to 4.2 V with voltage ripple lower than 6 inV. The pixel reset time is reduced to 1.14 ns in dark. Image smear due to non-completely reset is elIminated and the image signal swing range is enlarged. The charge pump is successfully embedded in a CMOS image sensor chip with 0.3 × 10^6 pixels.     

快速稳定的CMOS电荷泵电路的设计

基于交叉耦合NMOS单元,提出了一种低压、快速稳定的CMOS电荷泵电路.一个二极管连接的NMOS管与自举电容相并联,对电路进行预充电,从而改善了电荷泵电路的稳定建立特性.PMOS串联开关用于将信号传输到下一级.仿真结果表明,4级电荷泵的最大输出电压为7.41 V,建立时间为0.85 μs.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

一种基于动态阈值NMOS的1.2 V CMOS模拟乘法器

分析了以动态阈值NMOS晶体管作为输入信号的输入晶体管,利用4个动态阈值NMOS和2个有源电阻设计和实现的一种1.2 V低功耗CMOS模拟乘法器电路。该电路具有节省输入晶体管数目、偏置晶体管和偏置电路,以及性能指标优良的特点。其主要参数指标达到:一、三次谐波差值40 dB,输出信号频带宽度375 MHz,平均电源电流约30 μA,动态功耗约36 μW。可直接应用于低功耗通信集成电路设计。     

A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

A self-boost charge pump topology for a gate drive high-side power supply

A self-boost charge pump topology is presented for a floating high-side gate drive power supply that features high voltage and current capabilities for use in integrated power electronic modules (IPEMs). The transformerless topology uses a small capacitor to transfer energy to the high-side switch from a single power supply referred to the negative rail. Unlike conventional bootstrap power supplies, no switching of the main phase-leg switches is required to provide power continuously to the high-side gate drive, even if the high-side switch is permanently on. Additional advantages include low parts-count and simple control requirements. A piecewise linear model of the self-boost charge pump is derived and the circuit's operating characteristics are analyzed. Simulation and experimental results are provided to verify the desired operation of the new charge pump circuit. Guidelines are provided to assist with circuit component selection in new applications.     

一种应用开关电容分压的电源电压检测电路

提出了一种基于标准CMOS工艺的电压检测(Voltage Detector, VD)电路,具有高集成度、低功耗、检测点多档位可调节的特点。开关电容(Switched Capacitor, SC)电路仅需一个低频时钟即可提供准确的电源分压,在低功耗应用中可以有效替代传统电阻分压。在3.3V电源电压的MCU应用中,电压检测电路仅消耗几百nA的电流,对时钟变化不敏感（低频时钟频率变化范围4 kHz~40 kHz）,并且响应时间在一个时钟周期内     

A 70 mΩ intelligent high side switch with full diagnostics

A new, smart power switch for industrial, automotive, and computer applications developed in BCD (Bipolar, CMOS, DMOS) technology is described. It consists of an on-chip 70 mΩ power DMOS transistor connected in high side configuration and its driver makes the device virtually indestructible and suitable to drive any kind of load with an output current of 2.5 A. If the load is inductive, an internal voltage clamp allows fast demagnetization down to 55 V below the supply voltage. The device includes novel structures for the driver, the fully integrated charge pump circuit, and its oscillator. These circuits have specifically been designed to reduce electromagnetic interference (EMI) thanks to an accurate control of the output voltage slope and the reduction of the output voltage ripple caused by the charge pump itself. An innovative open load circuit allows the detection of the open load condition with high precision (3 mA ±10% within the temperature range from -25 to 150°C and including process spreads). Furthermore, the device protects the load from ground disconnection and is compatible with the new IEC standards concerning burst and surge tests. The quiescent current has also been reduced to 600 μA. Diagnostics for CPU feedback is externally available from the chip by two dedicated pins when the following fault conditions occur: open load, overload and short circuit to ground or to the supply voltage, overtemperature, and undervoltage supply     

一种单片低功耗电荷泵电源管理电路的设计

基于0.6 μm BiCMOS工艺,设计了一款高精度电荷泵电源管理芯片.该芯片利用2倍压电荷泵电源转换原理,芯片内部集成了具有优异频率响应的振荡器电容,施密特触发器提供内部精准频率,PFM调制提供稳定的输出电压.测试结果表明,芯片输入电压范围为2.7～5.5V,输出电压为5V,电压纹波小于20 mV,内部振荡频率为700 kHz,低功耗模式时电流仅为6.73 μA.