具有P型浮空区的槽栅IGBT结构

本文提出了一种具有P型浮空层的新型槽栅IGBT结构,它是在之前所提的一种积累层沟道控制的槽栅IGBT(TAC-IGBT)基础之上引入了一浮空P型层。此结构在维持原有TAC-IGBT低的正向导通压降和更大正向偏置安全工作区（FBSOA）的同时,减小了器件的泄漏电流,提高了器件的击穿电压,也使得器件的短路安全工作区大大提高,且制造简单,设计裕度增大。仿真结果表明：对于1200V的IGBT器件,具有P型浮空层的新型槽栅IGBT结构漏电比TAC-IGBT小近一个量级,击穿电压提高近150V。     

一种积累型沟道的半超结结构绝缘栅双极型晶体管

A high performance trench insulated gate bipolar transistor which combines a semi-superjunction struc- ture and an accumulation channel （sSJTAC-IGBT） is proposed for the first time. Compared with the TAC-IGBT, the new device not only retains the advantages of the accumulation channel, but also obtains a larger breakdown voltage （BV）, a faster turn-off speed and a smaller saturation current level while keeping the on-state voltage drop lower as the TAC-IGBT does as well. Therefore, the new structure enlarges the short circuit safe operating area （SCSOA） and reduces the energy loss during the turn-off process.     

Shielding region effects on a trench gate IGBT

In this paper we introduced the shielding region concept in order to relieve the electric field concentrated on the trench bottom corner. The shielded trench gate insulated gate bipolar transistor (IGBT) is a trench gate IGBT with a P+shielding region located in the bottom of a trench gate. By simulation results, we verified that a shielding region reduced the electric fields not only in the gate oxide but also in the P-base region. Compared with conventional trench gate IGBT, about 33% increment of forward breakdown voltages are achieved, but little forward voltage drop, which causes on-state loss to be increased by about 0.06 V in the shielded trench gate IGBT.     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

具有积累层沟道的槽栅IGBT结构

提出了一种具有积累层沟道的槽栅IGBT结构。仿真结果表明：在阻断电压为1200V,集电极电流密度为100 A/cm2,温度分别为300K和400K下的情况下,积累层沟道槽栅IGBT的正向压降分别为1.5V 和2V而常规槽栅IGBT分别为1.7V和2.4V。新结构比常规槽栅IGBT具有更低的开态压降和更大的正向安全工作区。文中同时分析了积累层沟道槽栅IGBT的阻断特性和关断特性。     

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simu-lation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm~2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K,respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.     

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I-V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14 V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600 V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.     

具有沟槽阳极短路的新型沟槽栅场截止绝缘栅双极晶体管

文章提出了一种新型的具有沟槽阳极短路的槽栅场截止型绝缘栅双极晶体管结构。通过引入沟槽短路阳极结构,器件的击穿电压得到了明显提高。仿真结果显示,相比于传统的场截止型绝缘栅双极晶体管,新结构提高了19.5 %的击穿电压,而且新结构具有更小的漏电流。在电流密度为150 A/cm2 时,新结构虽然提高了近百分之九的导通压降,但是关断时间只有传统结构的一半。此外,新结构导通时没有负阻效应。因此,新结构具有更好的关断功耗与导通压降的折中关系。     

A New SOI LDMOSFET Structure with a Trench in the Drift Region for a PDP Scan Driver IC

To improve the characteristics of breakdown voltage and specific on‐resistance, we propose a new structure for a LDMOSFET for a PDP scan driver IC based on silicon‐on‐insulator with a trench under the gate in the drift region. The trench reduces the electric field at the silicon surface under the gate edge in the drift region when the concentration of the drift region is high, and thereby increases the breakdown voltage and reduces the specific on‐resistance. The breakdown voltage and the specific on‐resistance of the fabricated device is 352 V and 18.8 m·cm² with a threshold voltage of 1.0 V. The breakdown voltage of the device in the on‐state is over 200 V and the saturation current at V_gs=5 V and V_ds=20 V is 16 mA with a gate width of 150 µm.     

Trench SJ IGBT 的仿真研究

本文对沟槽型超结绝缘栅双极晶体管(trench SJ IGBT)进行了全面的分析,并通过Sentaurus TCAD仿真软件将其与沟槽型场截止绝缘栅双极晶体管(trench FS IGBT)进行了详尽的对比,仿真结果显示,在相同的条件下与trench FS IGBT 相比,trench SJ IGBT 的击穿电压提高了100 V,饱和导通压降降低了0.2 V,关断损耗减少了50%。最后,文章研究了电荷不平衡对trench SJ IGBT 的动静态参数的影响。对各参数和它们对电荷不平衡的灵敏度之间的折中进行了讨论。     

高压IGBT线性变窄场限环终端设计

为使3300 V及以上电压等级绝缘栅双极型晶体管(IGBT)的工作结温达到150℃以上,设计了一种具有高结终端效率、结构简单且工艺可实现的线性变窄场限环(LNFLR)终端结构。采用TCAD软件对这种终端结构的击穿电压、电场分布和击穿电流等进行了仿真,调整环宽、环间距及线性变窄的公差值等结构参数以获得最优的电场分布,重点对比了高环掺杂浓度和低环掺杂浓度两种情况下LNFLR终端的阻断特性。仿真结果表明,低环掺杂浓度的LNFLR终端具有更高的击穿电压。进一步通过折中击穿电压和终端宽度,采用LNFLR终端的3300 V IGBT器件可以实现4500 V以上的终端耐压,而终端宽度只有700μm,相对于标准的场限环场板(FLRFP)终端缩小了50%。     

1 200 V沟槽栅场截止型IGBT终端设计

利用二维半导体工艺及器件模拟工具,从结掺杂浓度、P阱与P环间距、P环尺寸控制3个方面分析了半绝缘多晶硅终端结构的击穿电压,提出了应用于1 200 V沟槽栅场截止型IGBT的终端解决方案。从结的深度和终端长度两方面,将SIPOS终端技术与标准的场环场板终端技术进行了对比。结果表明,采用SIPOS终端结构并结合降低表面场技术,使得终端尺寸有效减小了58%,并且,采用SIPOS技术的终端区域击穿电压受结深的影响较小,有利于实际制造工艺的控制和IGBT器件稳定性的提升。     

A novel gate geometry for the IGBT: the trench planar insulatedgate bipolar transistor (TPIGBT)

This letter demonstrates a simple way to improve the performance of a planar, fine lithography insulated gate bipolar transistor (IGBT), by incorporating a trench gate between the cathode cells. The results of this new trench-planar IGBT (TPIGBT) clearly demonstrate a significant reduction in the voltage drop without degrading the breakdown voltage. The switching analysis indicates that the TPIGBT represents a good trade-off between planar and trench structures. By separating the trench gate requirements away from the cathode cells, the technology development cycle and costs can be reduced. Furthermore, the reduced cell-width and the shallow trench presents TPIGBT as a cost-effective structure for high-voltage applications     

A novel TFS-IGBT with a super junction floating layer

A novel trench field stop (TFS) IGBT with a super junction (SJ) floating layer (SJ TFS-IGBT) is proposed.This IGBT presents a high blocking voltage (>1200 V), low on-state voltage drop and fast turn-off capability. A SJ floating layer with a high doping concentration introduces a new electric field peak at the anode side and optimizes carrier distribution, which will improve the breakdown voltage in the off-state and decrease the energy loss in the on-state/switching state for the SJ TFS-IGBT. A low on-state voltage (VF) and a high breakdown voltage (BV) can be achieved by increasing the thickness of the SJ floating layer under the condition of exact charge balance. A low turn-off loss can be achieved by decreasing the concentration of the P-anode. Simulation results show that the BV is enhanced by 100 V, VF is decreased by 0.33 V (at 100 A/cm2) and the turn-off time is shortened by 60%, compared with conventional TFS-IGBTs.     

一种带有超结浮空层的槽栅场阻IGBT

本文提出了一种带有超结浮空层的槽栅场阻IGBT,它具有高的击穿电压(>1200V),低的正向压降和快速的关断能力。高掺杂的 SJ 浮空层在阳极侧引入了电场峰的同时优化了器件内载流子分布,带来关态击穿电压提高,开态、开关态能量损耗减少等好处。在保持电荷平衡的前提下,增加 SJ 浮空层的厚度可以提高击穿电压和降低正向压降,降低 P 型阳极浓度可以减少关断损耗。与传统结构相比,新结构击穿电压提高了100V,正向压降降低了0.33V（电流密度为100A/cm2）,关断时间缩短了60%。     

新型双RESURF TG-LDMOS器件结构

研究了采用双RESURF技术的槽栅横向双扩散MOSFET（DRTG-LDMOS），讨论了双RESURF技术对击穿电压的影响，以及DRTG-LDMOS的电容特性，与传统的槽栅器件结构相比，新结构在相同的漂移长度和导通电阻下，击穿电压提高了30V，并表现出优异的频率特性；     

3300V沟槽栅IGBT的衬底材料的优化设计

使用TCAD仿真软件对3 300 V沟槽栅IGBT的静态特性进行了仿真设计.重点研究了衬底材料参数、沟槽结构对器件击穿电压、电场峰值等参数的影响.仿真结果表明,随衬底电阻率增加,击穿电压增加,饱和电压和拐角位置电场峰值无明显变化;随衬底厚度增加,击穿电压增加,饱和电压增加,拐角位置电场峰值降低;随沟槽宽度增加,饱和电压降低,击穿电压和拐角位置电场峰值无明显变化;随沟槽深度增加,饱和电压降低,击穿电压无明显变化,拐角位置电场峰值增加;随沟槽拐角位置半径增加,击穿电压和饱和电压无明显变化,但拐角位置电场峰值减小.选择合适的衬底材料对仿真结果进行实验验证,实验结果与仿真结果相符,制备的IGBT芯片击穿电压为4 128 V,饱和电压约为2.18 V.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

300V以上硅基新型JBS肖特基二极管的制备

为了在保留传统肖特基二极管正向压降低、电流密度大优点的基础上,使其反向击穿电压提高到了300 v以上,我们采用硅材料做为衬底,肖特基结区采用蜂房结构,终端采用两道场限环结构加一道切断环结构,所制备的肖特基二极管在正向电流10A时,正向压降仅为0.79 V;同时在施加300 V反向电压时,反向漏电流在5μA以下.     

A CMOS compatible lateral emitter switched thyristor with enhancedturn-on capability

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n^- drift region and the n⁺ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3 μm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm² with 5 V gate voltage