一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

一种低功耗2D DCT/IDCT处理器设计

设计了一种低功耗的2D DCT/IDCT处理器。为了降低功耗,设计基于行列分解的结构,采用了Loeffler的DCT/IDCT快速算法,并使用了零输入旁路、门控时钟、截断处理等技术,在满足设计需求的基础上降低了系统的功耗。常系数乘法器是该处理器的一个重要部件,文中基于并行乘法器结构设计了一种新型的低功耗常系数乘法器,它采用了CSD编码、Wallace Tree乘法算法,结合采用了截断处理、变数校正的优化技术,使得2D DCT/IDCT处理器整体性能有较大提高。设计的时钟频率为100 MHz,可以满足MPEG2 MP@HL实时解码的应用。采用SMIC0.18μm工艺进行综合,该2D DCT/IDCT处理器的面积为341 212μm2,功耗为14.971 mW。通过与其他结构的2DDCT/IDCT处理器设计分析与比较,在满足MPEG2 MP@HL实时解码应用的同时,实现了较低的功耗。     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

A Class‐D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class‐D audio amplifier for a digital hearing aid is described. The class‐D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma‐delta modulator (SDM), and an analog SDM, along with an H‐bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class‐D amplifier is implemented in a 0.13‐μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class‐D amplifier consumes 304 μW from a 1.2‐V power supply.     

一种8位高速折叠内插A/D转换器的设计

介绍了基于0.35μm BiCMOS工艺的8位高速A/D转换器,采用独特的折叠和内插结构,在大大降低成本、功耗的同时,既能保证超高转换速率,又能达到较高的静态和动态指标。在采样率1GS/s和模拟输入差分250mV(Vp-p)、484MHz条件下进行测试,SFDR高达56dB,SNR高达45.5dB;在3.3V电源电压下,功耗为800mW。     

用于12 bit 40 MS/s低功耗流水线ADC的采样保持电路

设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.     

A stereo audio chip using approximate processing for decimation andinterpolation filters

A stereo audio chip uses approximate processing techniques in the digital decimation and interpolation filters to reduce its active power dissipation. One pair of analog-to-digital (A/D) converters and one pair of digital-to-analog (D/A) converters have been integrated in a die area of 10.22 mm² in a 0.5 μm CMOS technology. The total power dissipation of these converters without power management is 200 mW when operated from a 5-V power supply. When the signal is fully active, power reductions of 36% for decimation and 17% for interpolation over fixed-order filters are demonstrated. When the signal is 40 dB below overload, power reductions of 67% for decimation and 44% for interpolation over fixed-order filters are observed. The power reductions are 83.1% for A/D converters, and 82.7% for D/A converters, when the signal is silent for a period of time     

一种基于0.13m CMOS工艺的10位SAR A/D转换器

基于SMIC0.13μm CMOS1P6M Logic工艺,采用一种新型R-C组合式D/A转换结构、伪差分比较结构以及低功耗电平转换结构设计了一种用于多电源SoC的10位8通道逐次逼近型A/D转换器。在3.3V模拟电源电压和1.2V数字电源电压下,测得DNL和INL分别为0.31LSB和0.63LSB。当采样频率为1MS/s,输入信号频率为490kHz时,测得的SFDR为67.33dB,ENOB为9.48bits,功耗为3.25mW。该A/D转换器版图面积为318μm×270μm,能直接应用于嵌入式多电源SoC。     

一种12位50MS/s CMOS流水线A/D转换器

采用TSMC 0.18μm 1P6M工艺设计了一个12位50 MS/s流水线A/D转换器（ADC）。为了减小失真和降低功耗,该ADC利用余量增益放大电路（MDAC）内建的采样保持功能,去掉了传统的前端采样保持电路;采用时间常数匹配技术,保证输入高频信号时,ADC依然能有较好的线性度;利用数字校正电路降低了ADC对比较器失调的敏感性。使用Cadence Spectre对电路进行仿真。结果表明,输入耐奎斯特频率的信号时,电路SNDR达到72.19 dB,SFDR达到88.23 dB。当输入频率为50 MHz的信号时,SFDR依然有80.51 dB。使用1.8 V电源电压供电,在50 MHz采样率下,ADC功耗为128 mW。     

适用于射频识别标签的64-kbit嵌入式阻变存储器

设计并实现了一颗适用于射频识别(RFID)标签的低功耗嵌入式64-kbit阻变存储器芯片.提出了新型的带尖峰电流控制功能的高压稳压电路,在提供稳定编程电压的同时降低了芯片电源上的瞬态大电流,改善了存储器电路的可靠性;设计了适用于2T2R(2 Transistors and 2 Resistive cells)单元的敏感...     

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design chal-lenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm~2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.     

InGaAs/AlGaAs半导体激光器二维阵列

用金属有机化合物气相淀积 (MOCVD)技术外延生长了InGaAs/AlGaAs分别限制应变单量子阱激光器材料。利用该材料制成半导体激光器一维线阵列 ,然后再串联组装成二维阵列 ,在 1 0 0 0 μs的输入脉宽下 ,输出峰值功率达到 730W (77A) ,输出光功率密度为 4 87W/cm2 ,中心激射波长为 90 3nm ,光谱半宽 (FWHM )为 4 4nm。在此条件下可以稳定工作 86 0 0h以上     

一种低噪声、高电源抑制的低压降稳压器

实现了一种低噪声、高电源抑制(PSR)的低压降线性稳压器。设计了一个新型的低温度系数高电源抑制的带隙基准源,这个基准源可以为稳压电路提供参考电压。采用带有低通滤波器的预调制电路来降低稳压器的输出噪声和高频电源行波干扰。测试结果表明,该稳压器的线性调整率为0.57mV/V,负载调整率为0.1mV/mA,100kHz下的交流电源抑制为-60dB。在10Hz～1MHz频率范围内,仿真得到的总输出噪声只有4μVrmss。该稳压器采用上华CSMC0.6μm、5V混合信号CMOS工艺设计,有效芯片面积为600μm×560μm。     

14位1.5625MHz的ΣΔA/D中的降采样低通滤波器的设计

介绍了带宽为 70 0kHz ,14 bitΣΔ模数转换器中的降采样低通滤波器的设计。在整个滤波器的设计中 ,从结构上和硬件实现上入手 ,对电路结构进行优化 ,减小电路实现的复杂性 ,从而降低功耗和面积。在此基础上 ,完成了电路设计 ,用 0 .6 μmCMOS工艺综合实现 ,仿真结果显示 ,性能满足设计指标。     

355nm紫外激光器加工多层柔性线路板盲孔

采用输出功率10 W的355 nm Nd:YVO_4激光器对4层柔性线路板(FPC)进行了盲孔加工实验.重点研究和分析了不同加工方式、功率密度、扫描间距、开/关激光延时等参数对加工结果的影响.得到的优化工艺参数为:第一次采用加工功率3.9 W、频率80 kHz、扫描速度50 mm/s、开/关激光延时20 μs/110 μs、扫描间距18 μm,第二次将加工功率降到1.4 W,其他参数不变,此时,加工盲孔的效果最为理想,重铸层粗糙度为0.889 66 μm,孔底粗糙度为1.063μm,给出了孔底表面的SEM图和针式台阶仪测量的盲孔底面三维轮廓和切面二维轮廓图.     

A 4 W K-band GaAs MMIC power amplifier with 22 dB gain

A 4 W K-band AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) mono-lithic microwave integrated circuit (MMIC) high power amplifier (PA) is reported. This amplifier is designed to fully match for a 50 Ω input and output impedance based on the 0.15 μm power PHEMT process. Under the condition of 5.6 V and 2.6 A DC bias, the amplifier has achieved a 22 dB small-signal gain, better than a 13 dB input return loss,and 36 dBm saturation power with 25% PAE from 19 to 22 GHz.     

一种低工艺敏感度,高PSRR带隙基准源

实现了一种高精度带隙基准源,该基准源在预调节电路中应用了电源行波减法技术,显著改善了输出电压的电源抑制比。提出了采用电流负反馈技术稳定预调节电路电流的方法,降低了带隙基准的温度特性和电源抑制比对阈值电压的敏感度。考虑晶体管阈值电压发生±20%变化的情况下,仿真得到的基准源的温度系数和电源抑制比变化分别只有0.11ppm和7dB。测试结果表明,该基准源在-20～100℃的范围内的有效温度系数为25.7ppm/℃,低频电源抑制比为-68dB。其功耗为0.5mW,采用中芯国际0.35μm5-V混合信号CMOS工艺实现,有效芯片面积为300μm×200μm。     

D类音频功放中电流控制振荡器的设计

基于N阱0．5μmDPTM CMOS工艺,完成了D类音频功放中电流控制振荡器的设计。首先分析了电流控制振荡器的工作原理,然后着重介绍了振荡器的设计。仿真结果表明,5V电源电压下振荡器的频率为250kHz,温度在-40-120℃,电源电压在3-5V范围内,频率随温度和电源电压的改变很小,仅为4％。该电路应用于某款D类音频功放芯片。