低相噪硅雷达射频频率源的研究与设计

分析了频率源中各个模块的噪声传递函数,确定影响近端噪声的模块分别是鉴频鉴相器-电荷泵(PFD-CP)、分频器;在默认分频器相位噪声为-158dBc/Hz,通过matlab建模推断,需要PFD-CP模块在10kHz频偏处的输入噪声达到-143dBc/Hz,才能实现频率源输出信号在10kHz频偏处相位噪声-107dBc/Hz。采用0.18μmSiGe BiCMOS工艺,设计了整块芯片,着重优化了PFD-CP模块的输入噪声,经过spectre仿真,PFD-CP模块的输入噪声为-146dBc/Hz,经过实测,输出信号在10kHz频偏处相位噪声为-108dBc/Hz,达到设计预期。     

射频MEMS封装振荡器的稳定性研究

文章介绍了一种由MEMS圆盘谐振器和低噪声反馈电路构成的射频振荡器。MEMS谐振器具备高Q值,使得振荡器表现出良好的频率稳定性和低相位噪声。采用低成本的金锡键合工艺对双端口谐振器封装后,进一步提升了频率稳定性。低噪声电路由两级放大组成,在提供足够增益的情况下,提升了相位噪声性能。之后测试得到的相位噪声分别是在1 kHz 频偏处为-96 dBc/Hz,噪底 -128 dBc/Hz 。中期稳定性和阿伦方差的测试结果分别为±4 ppm和10 ppb。这些结果均表明,该振荡器在新一代无线通信中有广阔的应用前景。     

基于单片机控制的频率综合器设计

以ADF4360芯片为核心,设计实现了频率综合器作为1.95 GHz一次变频超外差射频接收机的本振部分,并制作了单片机控制电路。经测试,可以在1.6GHz～1.95GHz范围内以0.5MHz为步长调节输出本振信号频率。在频率为1.9GHz时,相位噪声为-68dBc/Hz（1kHzoffset）、-71dBc/Hz（10kHz offset）、-110dBc/Hz（100kHz offset）、-115dBc/Hz（1MHz off-set）。频率偏差小于50kHz。     

一种基于偏移源的频率合成技术分析

针对一种基于偏移源的频率合成技术,建立了锁相环(PLL)线性模型,对相位噪声和杂散信号性能进行分析。从分析结果看,在锁相环反馈支路中使用一个偏移源将压控振荡器(VCO)输出信号下混频至一个较低的中频,从而将锁相环的环路分频比大大降低,使改善后的锁相环噪底达到-135 dBc/Hz。介绍了偏移源和主环的关键合成技术,结合工程应用设计的基于偏移源的C频段频率合成器,相位噪声偏离载波10 kHz处≤-99 dBc/Hz,偏离载波100 kHz处≤-116 dBc/Hz,杂散小于-70 dBc。     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

A Quantization Noise Suppression Technique for$DeltaSigma$Fractional-$N$Frequency Synthesizers

The first circuit implementation of quantization noise suppression technique for DeltaSigma fractional- N frequency synthesizers using reduced step size of frequency dividers is presented in this paper. This technique is based on a 1/1.5 divider cell which can reduce the step size of the frequency divider to 0.5 and thus the reduced step size suppresses the quantization noise by 6 dB. This frequency synthesizer is intended for a WLAN 802.11a/WiMAX 802.16e transceiver. This chip is implemented in a 0.18-mum CMOS process and the die size is 1.23 mm times 0.83 mm. The power consumption is 47.8 mW. The in-band phase noise of -100 dBc/Hz at 10 kHz offset and out-of-band phase noise of -124 dBc/Hz at 1MHz offset are measured with a loop bandwidth of 200 kHz. The frequency resolution is less than 1 Hz and the lock time is smaller than 10 mus     

Low phase noise heterojunction bipolar transistor oscillator

A low phase noise, heterojunction bipolar transistor (HBT) oscillator has been designed and fabricated for operation at X-band. The common emitter oscillator employs a high-Q dielectric resonator as the parallel feedback element between the base and collector terminals. Series capacitive feedback is used in the emitter to enhance the oscillator's negative output impedance. Single-sideband FM noise levels of -76 dBc/Hz and -102 dBc/Hz have been achieved at 1 kHz and 10 kHz frequency offsets, respectively, for an 11.06 GHz carrier frequency. This is one of the lowest phase noise levels ever reported for an X-band solid-state transistor oscillator.<>     

A 3.96 GHz phase-locked loop for mode.1 MB-OFDM UWB hopping carrier generation

PLL achieves a phase noise of-70 dBc/Hz at 10 kHz offset and -113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than -68 dBc.     

新型复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT低相位噪声微波单片集成压控振荡器

设计并研制了一种新型复合沟道Al0.3Ga0.7N/Al0.05Ga0.95N/GaN HEMT(CC-HEMT)微波单片集成压控振荡器(VCO),且测试了电路的性能.CC-HEMT的栅长为1μm,栅宽为100μm.叉指金属-半导体-金属(MSM)变容二极管被设计用于调谐VCO频率.为提高螺旋电感的Q值,聚酰亚胺介质被插入在电感金属层与外延在蓝宝石上GaN层之间.当CC-HEMT的直流偏置为Vgs=-3V,Vds=6V,变容二极管的调谐电压从5.5V到8.5V时,VCO的频率变化从7.04GHz到7.29GHz,平均输出功率为10dBm,平均功率附加效率为10.4%.当加在变容二极管上电压为6.7V时,测得的相位噪声为-86.25dBc/Hz(在频偏100KHz时)和-108dB/Hz(在频偏1MHz时),这个结果也是整个调谐范围的平均值.据我们所知,这个相位噪声测试结果是文献报道中基于GaN HEMT单片VCO的最好结果.     

超低相位噪声超高速声表面波雷达频率综合器

介绍了一种新型的高性能雷达频率综合器的制作方法，即采用声表面波技术制作高性能的雷达频综器。采用这种方法成功地制造了Ｌ波段、Ｓ波段、Ｃ波段超低相位噪声超高速频率综合器。该类频综输出信号具有极低相位噪声（１．６ＧＨｚ处：单边带相位噪声Ｌｍ（１ｋＨｚ）＝－１２７ｄＢｃ／Ｈｚ；３．４ＧＨｚ处：Ｌｍ（１ｋＨｚ＝－１２２ｄＢｃ／Ｈｚ；６．８ＧＨｚ处：Ｌｍ（１ｋＨｚ）＝－１１６ｄＢｃ（Ｈｚ）、极短的频率切换时间（约１６０ｎｓ）、低杂波电平（Ｌ波段为－７０ｄＢ；Ｓ波段为－６５ｄＢ；Ｃ波段为－６０ｄＢ）、较多频点（５１点）等多项优异性能。同时，该频综通过了各项环境试验的考核，且长期工作性能稳定。     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

一种钽酸锂压控振荡器的设计与实现

该文使用具有低电容比、宽调谐范围的钽酸锂晶体设计了一巴特勒共基低相位噪声压控振荡器,此设计在寻求高有载品质因数QL的同时保持了振荡器的输出功率。使用的钽酸锂晶体的无载品质因数Q0约为1.24×103,其频率为10.727MHz。设计出的巴特勒振荡器QL≈33%Q0,输出功率约为11dBm。不加压控的情况下,实际测得该振荡器的相位噪声结果为-85dBc/Hz@10 Hz和-145dBc/Hz@1kHz。在此基础上,增加一变容二极管作为压控元件设计了钽酸锂压控振荡器,在2~10 V范围内,测得控制电压压控斜率约为86.6×10-6/V,相位噪声测试结果优于-82dBc/Hz@10Hz和-142dBc/Hz@1kHz,实现了具有宽调谐范围的低相位噪声钽酸锂振荡器的设计。     

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO withwide-band low-noise automatic amplitude control loop

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 μA are drawn by the AAC circuit     

Quasi-planar K-band push-push low phase noise oscillator stabilized by cavity resonator

The results of developing a K-band (24 GHz) push-push low phase noise transistor oscillator have been presented. This oscillator is stabilized by a rectangular resonant metallic cavity. The power level of output signal is ?9.5 dBm, the fundamental harmonic suppression is 21 dB. Single sideband (SSB) phase noise spectral density of ?98 dBc/Hz at 10 kHz and ?128 dBc/Hz at 100 kHz offset from the carrier frequency is at the level of dielectric resonator oscillators (DRO) scaled to the same frequency. The oscillator features a compact size, low cost quazi-planar design and it is built using commercially available off the shelf parts.     

基于Phase-Refining技术的微波宽带频率合成器

为改善宽带频率合成器的相位噪声,提出一种基于Phase-Refining技术的微波宽带频率合成器结构与一种对其相位噪声的准确分析方法。首先,根据线性传递函数与叠加原理得到该频率合成器的相位噪声解析模型,通过对振荡器实测相位噪声谱型进行曲线拟合并带入模型中来准确预测其相位噪声性能。分析表明,在级联偏置锁相环中,整个输出频率范围内都可通过将反馈分频比最小化来改善其环路带宽内的相位噪声。实验结果表明,该频率合成器的输出频率范围为2.1~5.6 GHz,频率步进为1 Hz,当输出为2.1 GHz与5.6 GHz时,在频偏10 kHz处的相位噪声分别为-114.7 dBc/Hz与-108.2 dBc/Hz,其相位噪声测试结果与分析计算结果相吻合。     

基于高次谐波体声波谐振器的微波振荡器设计

基于高次谐波体声波谐振器(HBAR)的高品质因数(Q)值和多模谐振特性,设计了Colpitts和Pierce两种形式的微波振荡器。采用HBAR与LC元件组成谐振回路的方法,与放大电路构成反馈环路直接基频输出微波频段信号。Colpitts振荡器输出信号频率为980 MHz,信号输出功率为-4.92dBm,信号相位噪声达-119.64dBc/Hz@10kHz;Pierce振荡电路输出信号频率达到2.962GHz,信号输出功率为-9.77dBm,信号相位噪声达-112.30dBc/Hz@10kHz。     

U波段小数分频锁相环型频率综合器

使用0.18μm1.8VCMOS工艺实现了U波段小数分频锁相环型频率综合器,除压控振荡器(VCO)的调谐电感和锁相环路的无源滤波器外,其他模块都集成在片内。锁相环采用了带有开关电容阵列(SCA)的LC-VCO实现了宽频范围,使用3阶MASHΔ-Σ调制技术进行噪声整形降低了带内噪声。测试结果表明,频率综合器频率范围达到650～920MHz;波段内偏离中心频率100kHz处的相位噪声为-82dBc/Hz,1MHz处的相位噪声为-121dBc/Hz;最小频率分辨率为15Hz;在1.8V工作电压下,功耗为22mW。     

0.35m SiGe BiCMOS工艺Colpitts振荡器

应用标准0.35μm SiGeBiCMOS工艺设计一个Colpitts压控振荡器并流片。采用线性时变模型(LTV)分析振荡器的相位噪声。在3.3V电源电压下,压控振荡器的频率范围覆盖340～400MHz,10kHz频偏处相位噪声为-91dBc/Hz,输出功率-3dBm。相位噪声的测试结果与理论计算结果符合较好。芯片面积550μm×300μm。