应用于5GHz频段带ESD保护的可变增益低噪声放大器

本文给出了应用于5GHz频段的可变增益低噪声放大器。详细分析了输入寄生电容对源极电感负反馈低噪声放大器的影响,给出了一种新的ESD和LNA联合设计的方法,另外,通过在第二级中加入一个简单的反馈回路实现了增益的可变。测试结果表明： 可变增益低噪声放大器增益变化范围达25dB (-3.3dB～21.7dB),最大增益时噪声系数为2.8dB,最小增益时三阶截点为1dBm,在1.8V电源电压下功耗为9.9mW。     

一种带宽为3.8GHz，增益步长为0.1dB的可编程增益放大器

A broadband programmable gain amplifier（PGA） with a small gain step and low gain error has been designed in 0.13 m CMOS technology. The PGA was implemented with open-loop architecture to provide wide bandwidth. A two-stage gain control method, which consists of a resistor ladder attenuator and an active fine gain control stage, provides the small gain step. A look-up table based gain control method is introduced in the fine gain control stage to lower the gain error.The proposedPGAshows a decibel-linear variable gainfrom4 to20 dB with a gain step of 0.1 dB and a gain error less than˙0.05 dB. The 3-dB bandwidth and maximum IIP3 are 3.8 GHz and 17 dBm, respectively.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

1V高线性度2.4GHz CMOS低噪声放大器

讨论了低噪声放大器(LNA)在低电压、低功耗条件下的噪声优化及线性度提高技术.使用Chartered 0.25μm RF CMOS 工艺设计一个低电压折叠式共源共栅LNA.后仿真结果表明在1V电源下,2.36GHz处的噪声系数NF仅有1.32dB,正向增益S21为14.27dB,反射参数S11、S12、S22分别为 -20.65dB、-30.27dB、-24dB,1dB压缩点为-13.0dBm,三阶交调点IIP3为-0.06dBm,消耗的电流为8.19mA.     

Co-design method for dual-band low-noise amplifier and band-pass filter

A simple method for the design of two-dimensional circularly symmetric recursive digital filters is presented. This method makes use of a one-dimensional analogue filter and an additional zero-phase polynomial in the numerator to approximate a desired magnitude response. The number of coefficients required to be optimized is reduced and the stability of the filter can be guaranteed. Generally, moderately precise filters can be obtained using this design method.     

2.4 GHz、增益可控的CMOS低噪声放大器

介绍了一种基于 0 35 μmCMOS工艺、2 4GHz增益可控的低噪声放大器。从噪声优化、阻抗匹配及增益的角度详细分析了电路的设计方法 ,讨论了寄生效应对低噪声放大器性能的影响。仿真结果表明在考虑了高频寄生参数的情况下 ,低噪声放大器依然具有良好的性能指标 :在 2 4GHz工作频率下 ,3dB带宽为 6 6 0MHz,噪声系数NF为 1 5 8dB ,增益S2 1为 14dB ,匹配参数S11约为 - 13 2dB。     

CMOS毫米波低功耗超宽带共栅低噪声放大器

陈述了一个基于单端共栅与共源共栅级联结构的超宽带低噪声放大器(LNA).该LNA用标准90-nm RFCMOS工艺实现并具有如下特征:在28.5～39 GHz频段内测得的平坦增益大于10 dB;-3 dB带宽从27～42 GHz达到了15 GHz,这几乎覆盖了整个Ka带;最小噪声系数(NF)为4.2dB,平均NF在27 ～ 42 GHz频段内为5.1 dB;S11在整个测试频段内小于-11 dB.40 GHz处输入三阶交调点(IIP3)的测试值为+2 dBm.整个电路的直流功耗为5.3 mW.包括焊盘在内的芯片面积为0.58 mm×0.48 mm.     

A novel reconfigurable variable gain amplifier for a multi-mode multi-band receiver

This paper presents a novel approach for designing a reconfigurable variable gain amplifier(VGA) for the multi-mode multi-band receiver system RF front-end applications.The configuration,which is comprised of gain circuits,control circuit,DC offset cancellation circuit and mode switch circuit is proposed to save die area and power consumption with the function of multi-mode and multi-band through reusing.The VGA is realized in 0.18μm CMOS technology with 1.8 V power supply voltage providing a gain tuning...     

一种新颖的可应用于多模多频接收机可配置的可变增益放大器

本文阐述了一种新颖的可应用于多模多频接收机射频前端可配置的可变增益放大器的设计方法。可变增益放大器包括增益放大电路,控制电路,直流失调消除电路和模式转换电路四个部分。这种结构可以在保证多模多频应用的前提下通过硬件复用最大化来节省芯片面积和功耗。电路采用0.18 um CMOS 工艺,在1.8V的供电电压下可实现5dB 至87dB的动态范围,电路的带宽（所有增益下）大于80 MHz。此外,直流失调消除电路有效抑制了直流失调成分至小于40mV。整个电路的功耗小于3mA,面积为705um*100um。     

A 6-7 GHz, 40 dB receiver RF front-end with 4.5 dB minimum noise figure in 0.13μm CMOS for IR-UWB applications

A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP₃ of-11 dBm.The core receiver （without test buffer） consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm² area.     

CMOS single-ended-to-differential low-noise amplifier

In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 μm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180±1°. Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is −9.5 dB m while intermodulation intercept point is −3 dB m, dissipating 6 mA from 1.5 V supply voltage.     

2-4GHz波段低噪声放大器的仿真设计

利用pHEMT工艺设计了一个2-4GHz宽带微波单片低噪声放大器电路。本设计中采用了具有低噪声、较高关联增益、pHEMT技术设计的ATF-54143晶体管,电路采用二级级联放大的结构形式,利用微带电路实现输入输出和级间匹配．通过ADS软件提供的功能模块和优化环境对电路增益、噪声系数、驻波比、稳定系数等特性进行了研究设计。最终使得该LNA在2-4GHz波段内增益大于20dB,噪声小于1-2dB,输出电压驻波比小于2,达到了设计指标的要求。     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

CMOS宽带可变增益放大器

设计了一种CMOS宽带、低功耗可变增益放大器.在分析使用源极退化电阻的共源放大器高频特性基础上,通过加入频率补偿电容改变放大器的零极点分布,在不增加功耗的情况下扩展了带宽.分析了放大器在低增益下出现的增益尖峰现象并加以解决.使用跨导增强电路提高了放大器的线性度.两级可变增益放大器使用TSMC0.25μm CMOS工艺.仿真结果表明,放大器在3.3V电压下核心电路功耗为3.15mW,增益范围0～40dB;在负载为5pF电容时3dB带宽大于340MHz,输出三阶交调点高于3.5dBm.     

A CMOS 4.1 GHz two-stage cascode LNA with ESD protection

A 4.1 GHz two-stage cascode Low-Noise Amplifier (LNA) with Electro-Static Discharge (ESD) protection is presented in this paper. The LNA has been optimized using ESD and LNA co-design methodology to achieve a good performance. Post-layout simulation results exhibit a forward gain (S21) of about 21 dB, a reverse isolation (S12) of less than –18 dB, an input return loss (S11) of less than –16 dB, and an output return loss (S22) of less than –17 dB. Moreover, the Noise Figure (NF) is 2.6 dB. This design is implemented in TSMC0.18μm RF CMOS technology and the die area is 0.9 mm 0.9 mm.     

GNSS接收机带有滤波功能可变增益放大器的设计

传统GNSS前端接收机系统中,可变增益放大器（VGA）不具备滤波功能,大多数选用片外滤波,这样系统增益和集成度降低,而系统集成的波器选频性能有限。为此,设计一种具有滤波功能的可变增益放大器,采用0．5μmSiGe HBT工艺,可控增益单元与Gm-C滤波单元集成一体,并运用4晶体管回转器结构实现滤波。电路驱动电压为3.3V,电流为11．7mA。线性增益控制范围为-26～62dB,且电压控制范围为0．1．8V,最小增益下输入1dB压缩点为-4dBm。可变增益放大器电路不仅具备大的增益控制范围,而且中频46MHz处滤波性能良好,提高芯片的集成度．降低系统功耗。     

A CMOS vector lock-in amplifier for sensor applications

The design of an integrated lock-in amplifier is discussed, specifically conceived for the detection of low-level signals at a harmonic of the drive frequency in magnetically excited resonant structures. The circuit includes in-phase and quadrature analogue signal processing channels, whose outputs feed an integrated ΣΔ analogue to digital converter. The circuit can be operated in different configurations, depending on the application requirements: in particular, by combining the digitized outputs of the two channels, vector operation can be obtained. The entire analogue chain, including the ΣΔ modulator, was designed using fully differential elaboration. The circuit was developed in a , dual poly-Si, four metal layers analogue CMOS technology with high resistivity poly-Si option. Circuit performance is discussed on the basis of transistor-level simulations and measurement results.