一种获得四管CMOS图像传感器像素夹断电压的方法

提出了一种测试四管CMOS图像传感器像素夹断电压的方法。该方法是基于像素中势阱结构的变化能够对图像信号散粒噪声产生影响的假设。实验结果测得的夹断电压与理论预测相一致。该技术提供的实验方法不仅能够帮助设计四管CMOS图像传感器光电二极管的结构,而且也能优化像素生产工艺。     

The effect of size on photodiode pinch-off voltage for small pixel CMOS image sensors

The electron potential of a photodiode in a CMOS image sensor should be designed precisely since the charge capacity of the photodiode decreases as the pixel area shrinks. The pinch-off voltage of a photodiode, which also affects the electron capacity, is dependant on the doping profile of the pn junction as well as the size of the photodiode. The pinch-off voltage is lower in a smaller photodiode. A simple method that uses the lateral depletion of a photodiode for an estimate of the pinch-off voltage in small photodiodes is proposed, and is compared to the measured experimental data. Two constants are used to account for the doping profile and photodiode size. The measurement data shows the error of the estimation of the pinch-off voltage to be <0.05 V.     

CMOS数字像素传感器噪声研究

在研究CMOS数字像素传感器(DPS)噪声特性的基础上,利用脉冲宽度调制(PWM)原理建立了关于PWM DPS完善的系统噪声数学模型。相比于传统CMOS图像传感器噪声研究,该模型考虑了系统中各像素单元积分时间不同和像素级模数转换的特点,推导出总噪声表达式。研究表明,低照度时噪声由暗电流散粒噪声主导,光强大时主要来源为光电二极管散粒噪声。模型中光电二极管散粒噪声与光照无关、暗电流散粒噪声与光照有关。研究结果表明针对PWM DPS系统,适当增大节点电容和比较器参考电压、改善比较器失配可有效降低噪声。     

Noise in a CMOS digital pixel sensor

Based on the study of noise performance in CMOS digital pixel sensor(DPS),a mathematical model of noise is established with the pulse-width-modulation(PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region. In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator’s reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.     

Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10~(12) cm~(-2),an implant ...     

四管CMOS图像传感器中像素图像拖影的二维仿真与优化

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 10¹² cm^–2, an implant tilt of –2^o, a transfer gate channel doping dose of 3.0 × 10¹² cm^-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.     

CMOS图像传感器钳位光敏二极管夹断电压模型研究

A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson＇s equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.     

CMOS图像传感器中电荷非完全转移的影响分析

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size.Based on the emission current theory,a qualitative photoresponse model is established to the preliminary prediction.Further analysis of noise for incomplete charge transfer predicts the noise variation.The test pixels were fabricated in a specialized 0.18μm CMOS image sensor process and two different processes of buried N layer implantation are compared.The trend prediction corresponds with the test results,especially as it can distinguish an unobvious incomplete charge transfer.The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.     

CMOS有源光电传感器像素采集单元成像质量分析

针对CMOS光电二极管型有源像素采集单元中存在的拖影问题,从像素采集单元的工作原理入手,利用光电二极管的等效电路模型,对像素采集单元的光电转换状态和置位状态进行分析.得出造成拖影的根本原因是光电二极管置位后的电压与上一周期末光电二极管的光生电压有关.     

CMOS图像传感器及其研究

介绍了CMOS图像传感器的工作原理,比较了CCD图像传感器与CMOS图像传感器的优缺点,指出了CMOS图像传感器的技术问题和解决途径,综述了CMOS图像传感器的现状和发展趋势.     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

像素内两次曝光组合的宽动态范围CMOS图像传感器

提出了一种基于五管有源像素的宽动态范围CMOS图像传感器（CIS）,在像素内部的浮动节点处进行长曝光时间信号和短曝光时间信号的组合。通过优化像素操作,光电响应曲线得到了压缩,获得了宽动态范围图像。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明在两次曝光时间分别为2.4ms和70ns,30帧每秒的帧频条件下,传感器的动态范围达到80dB,满足安防监视系统的应用需求。     

Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18 μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.     

A new CMOS multimode digital pixel sensor dedicated to an implantable visual cortical stimulator

We describe in this paper a new CMOS multimode image pixel sensor (MIPS) dedicated to an implantable visual cortical stimulator. Each 16 μm × 16 μm pixel area contains a photodiode, with a fill factor of 22%, a comparator used to convert the pixel level from analog to digital (A/D) values and an 8-bit DRAM, resulting in a total of 44 transistors per pixel. The A/D conversions use one common digital to analog converter to deliver the voltage reference needed to determine the pixel voltage. Three selectable operation modes are combined in the proposed MIPS: A high dynamic range logarithmic mode, a linear integration mode, and a novel differential mode between two consecutive images. This last mode that allows 3D information is required for a visual cortical stimulator. A test chip has been fabricated in CMOS 0.18 μm technology and tested to validate the full operation of the different proposed modes. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec – ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International Conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 350 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE. Annie Trépanier received her Bachelor of Engineering Degree in Electrical Engineering in 2002 and her Master of Applied Sciences Degree in Microelectronics in 2005 from the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. She held a summer job at Nortel Networks and trained at Mindready. She is currently employed at Matrox, Montreal. Jean-Luc Trépanier received his Bachelor of Engineering Degree in Electrical Engineering in 2000 and his Master of Applied Sciences Degree in Microelectronics in 2003 from the Ecole Polytechnique de Montreal where he was a member of the Cortivision team in the Polystim Neurotechnologies Laboratory. He started his first company, Olyxia inc., where he developed the soon to be released Cute Spider VoIP Network. He is also the founder and CEO of Nexyrius inc. which develops a new generation of embedded systems. Yves Audet received his M.Sc. degree from a joint program between the University of Sherbrooke, QC, Canada and Université Joseph Fourier in Grenoble, France. He completed his Ph.D. at Simon Fraser University, BC, Canada. He has been working for three years in Research and Development with Mitel Corporation before being hired as assistant professor at école Polytechnique of Montreal, QC, Canada, in 2001. His research interests are CMOS sensor arrays and mixed signal circuits. Roula Ghannoum received her Bachelor of Engineering Degree in Computer and Communications Engineering from the Lebanese American University, Byblos—Lebanon, in July 2005. She is currently pursuing her Master of Applied Sciences in Microelectronics at the Ecole Polytechnique de Montreal as a member of the Cortivision team in the Polystim Neurotechnologies Laboratory working on image sensors as part of a global project that aims at restoring sight to the visually incapacitated.     

列级反馈降低复位噪声的CMOS图像传感器

提出了一种通过放大器和开关建立起反馈环路,基于列级反馈复位的低噪声CMOS图像传感器（CIS）。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明,通过对噪声带宽与反馈放大器的带宽匹配,在复位脉冲下降沿时间为6µs的条件下,传感器的复位噪声减少25dB,满足低照度高速的安防监视系统的应用需求。     

Reset noise reduction through column-level feedback reset in CMOS image sensors

A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.     

混合域实现图像块矩阵变换的CIS像素读出噪声分析

为了研究双存储像素的读出噪声对混合域实现图像块矩阵变换的CMOS图像传感器(CIS)产生的误差影响,对其进行噪声分析。结合双存储像素的工作时序,对实现图像块矩阵变换过程中由于多次采样和双路存储而增加的kTC噪声、源跟随器的1/f噪声和热噪声进行分析并建立数学模型,总结出双存储像素读出噪声对一次块矩阵变换的误差影响。以二维离散余弦变换为例,通过CHRT 0.35 m标准CMOS工艺电路仿真并结合matlab/simulink对比验证,得出增大存储电容、减小源跟随器宽长比可以降低由于像素读出噪声引起的误差。结果证明,此方法可以有效降低噪声,指导电路设计。     

基于估计方法的CMOS图像传感器列固定模式噪声校正方法

CMOS图像传感器的列固定模式噪声对图像质量的影响非常严重。在分析CMOS图像传感器固定模式噪声产生机理、噪声特性以及其在输出图像中的表现的基础上,提出了一种针对CMOS图像传感器中列固定模式噪声的校正方法。该方法利用CMOS图像采集系统对积分球发出的均匀平行光束进行多次采样并建模来对列固定模式噪声进行估计,然后将估计结果应用于CMOS图像硬件采集系统进行列固定模式噪声的校正,固定模式噪声的校正在FPGA中使用查找表方法实现。实验结果表明该方法可以有效消除列固定模式噪声,改善图像质量。     

CMOS图象传感器的原理及应用

CMOS图象传感器是多功能、高性能的摄象器件。本文详细介绍了其工作原理及其在微型摄象机、数码相机、医学等方面的应用     

CMOS图象传感器技术及其研究进展*

简要介绍了图象传感器的技术原理,比较了CCDs和CMOS图象传感器的技术特点。通过了解单片CMOS图象传感器的系统结构功能与器件类型,分析了单片CMOS图象传感器的性能要求与技术难点,总结出了提高性能所要进一步研究的关键问题。