Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues.     

Multistage network with globally controlled switching stages and its implementation using optical multi-interconnection modules

Plane-to-plane guided-wave-based interconnection modules are proposed as building blocks for scalable optoelectronic multistage interconnection networks (MINs). This approach leads naturally to a MIN paradigm based not on cascading switching stages containing several size-reduced crossbars, as in the shuffle-exchange (SE) networks, but on cascading permutation-reduced crossbars instead, one per stage. The interest of such an architecture lies in the control simplicity and scalability potential. Transparent circuit switching for permutation routing is possible in such an unbuffered "globally switched" multistage interconnection network (GSMIN). Preliminary experiments using fiber-based interconnection modules are presented. Performance analysis and simulation of a buffered GSMIN is also studied for packet routing purposes.     

Toroidal networks

The essential features of the toroidal network topology are examined, and its performance is evaluated. Some of the proposed applications of toroidal networks are described. Included in the discussion are metropolitan area network communication and multiprocessor interconnection, as well as the use of VLSI technology     

High-speed CMOS switch designs for free-space optoelectronic MIN's

We present the theory, experimental results, and analytical modeling of high-speed complementary metal-oxide-semiconductor (CMOS) switches, with a two-dimensional (2-D) layout, suitable for the implementation of packet-switched free-space optoelectronic multistage interconnection networks (MIN's). These switches are fully connected, bidirectional, and scaleable. The design is based on the implementation of a half-switch, which is a two-to-one multiplexer, using a 2-D layout. It introduces a novel self-routing concept, with contention detection and packet drop-and-resend capabilities. It uses three-valued logic, with 2.5 V being the third value for a 5 V power supply. Simulations show that for a 0.8-μm CMOS technology the switches can operate at speeds up to 250 Mb/s. Scaled-down versions of the switches have been successfully implemented in 2.0 μm CMOS. The analytical modeling of these switches show that large scale free-space optoelectronic MIN's using this concept could offer close to Terabit/sec throughput capabilities for very reasonable power and area figures. For example, a 4096 channel system could offer 256 Gb/s aggregate throughput for a total silicon area of about 18 cm² and a total power consumption (optics plus electronics) of about 90 W     

Recent VLSI neural networks in Japan

In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second).Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.     

Switching integrated broadband services by sort-banyan networks

Substantial attention has recently been given to the implementation of sort-banyan networks for switching asynchronous transfer mode (ATM) transmission links in a BISDN (broadband integrated service digital network) network. The author gives a three-dimensional view of the theory and implementation of switching, as well as variations of the basic scheme. ATM switches are classified as blocking versus nonblocking, unicast versus multicast, and input queued versus output queued. Sorting networks structured by a three-dimensional interconnection topology are studied. A sorting network, when coupled with a banyan routing network structured in three dimensions, becomes a self-routing and nonblocking switching network. This three-dimensional topology allows CMOS VLSI implementations of the subnetworks and interconnection of these subnetworks at a speed of 150 Mb/s and beyond. The sorting mechanism can also be used for output conflict resolution, subsequently making the switch suitable for ATM switching. Recent enhancements, which provide features such as parallelism, trunk grouping, and modularity, are also described. These features enhance the throughput/delay performance, provide better fault and synchronization tolerance, and enable more economical growth for switch size     

Banyan网输入输出排队的神经网络调度及其实现

Ｂａｎｙａｎ网是一种多级互联网络，它广泛地应用在ＡＴＭ交换结构中．Ｂａｎｙａｎ网输入排队的神经网络调度方法已有文章提出，但其硬件实现比较复杂．本文提出了一种Ｂａｎｙａｎ网输入输出排队的神经网络调度方法，它的硬件实现容易．计算机模拟结果表明，该调度方法是非常有效的．在此，还给出了该系统的硬件实现方法．     

基于3G-324M和SIP的3G可视电话互通研究

可视电话业务对网络带宽、时延抖动和丢包率都有较高的要求。中国目前的第三代移动通信技术（3G）网络制式使用不同的无线技术,这使得3G网络中可视电话业务在实现的技术方式上也不同。此处主要研究3G网络中基于3G-324M和SIP协议为基础的电路域和分组域可视电话的实现技术,包括控制协议和呼叫流程。同时针对各自不同的实现方式探讨互通的具体形式,在深入分析可视电话互通理论的基础上设计了互通网关的结构,这对于实现不同制式下的可视电话业务互通具有重要的参考价值。     

Buffered or unbuffered: a case study based onlogd(N,e,p) networks

Two implementation styles (buffered and unbuffered) have been used for constructing multistage interconnection networks for ATM switching. Conventional studies have shown that an unbuffered network, while having a simpler design, produces a lower throughput than a buffered network. But most of these studies, based on the assumption that each cell is routed independently (i.e. per-cell routing), ignored the out-of-sequence transmission problem of a buffered network in a virtual-channel environment. One way to keep the packet sequence for a buffered network without adding additional hardware is to fix the path for each virtual channel. We compute the throughput of this approach in designing nonblocking networks and compare it with that of the unbuffered approach. The base of our comparison is log_d(N,e,p) networks. The results show that a fixed-path-routing buffered network will have a throughput even lower than that of an unbuffered network     

DQDB城域网实现计算机局域网互连时的性能分析

DQDB城域网是实现现有通信网络向B-ISDN过渡的优选网络。本文分析了DQDB城域网用于计算机局域网互连时的排队性能;研究了报文长度、网络上下游负荷、带宽平衡参数和网络计数器级数对报文在缓存器中停留时间的影响。所得结果可为DQDB城域网的具体实现提供参考。     

Architecture, performance, and implementation of the tandem banyanfast packet switch

The authors propose a new space-division fast packet switch architecture based on banyan interconnection networks, called the tandem banyan switching fabric (TBSF). It consists of placing banyan networks in tandem, offering multiple paths from each input to each output, thus overcoming in a very simple way the effect of conflicts among packets (to which banyan networks are prone) and achieving output buffering. From a hardware implementation perspective, this architecture is simple in that it consists of several instances of only two VLSI chips, one implementing the banyan network and the other implementing the output buffer function. The basic structure and operation of the tandem banyan switching fabric are described, and its performance is discussed. The authors propose a modification to the basic structure which decreases the hardware complexity of the switch while maintaining its performance. An implementation of the banyan network using a high-performance BiCMOS sea-of-gates on 0.8-μm technology is reported     

An area-efficient topology for VLSI implementation of Viterbidecoders and other shuffle-exchange type structures

A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2-μm CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V_DD=4.75 V and T_A=70°C). The core of the chip (excluding pad cells) is 7.8×5.1 mm² and contains approximately 50000 transistors. The interconnection network occupies 32% of the area     

The selective extra stage butterfly

Multistage interconnection networks (MINs) have been used extensively as communication networks in parallel machines due to their high bandwidth, low diameter and constant degree switches. The fault-tolerance of multistage networks can be improved by simply adding extra stages to the network. A novel method of attaching the extra stages in MINs so that they are used in the absence of faults but not necessarily by all messages is suggested. Messages can adaptively select the shortest path to their destination or use one of the longer paths going through the extra stages. Performance results for the method (obtained through simulation), using various traffic loads both in the presence and absence of faults, are presented     

前均衡CMOS光电集成接收机概念的提出和模拟

提出了一种解决CMOS光电集成接收机灵敏度和速度问题的新方法--前均衡法,即在接收放大电路的前端对传输信号进行频率补偿,并分别采用并联谐振回路、三次阶梯网络和高通滤波器峰化技术设计了三种前均衡0.35μm CMOS光电集成接收机.其中,光电探测器选用面积为40μm×40μm的叉指型双光电二极管结构,实验测得该二极管的频率响应带宽为1.1GHz,结电容为0.95pF.对接收机的模拟结果表明:采用三次阶梯网络峰化技术的前均衡方案可有效提高光接收机的灵敏度和速度,并可实现灵敏度为-14dBm,3dB带宽为2GHz,BER为10-12的0.35μm CMOS光电集成接收机.     

Routing in optical multistage interconnection networks: a neuralnetwork solution

There has been much interest in using optics to implement computer interconnection networks. However, there has been little discussion of any renting methodologies besides those already used in electronics. In this paper, a neural network routing methodology is proposed that can generate control bits for a broad range of optical multistage interconnection networks (OMIN's). Though we present no optical implementation of this methodology, we illustrate its control for an optical interconnection network. These OMIN's can be used as communication media for distributed computing systems. The routing methodology makes use of an artificial neural network (ANN) that functions as a parallel computer for generating the routes. The neural network routing scheme can be applied to electrical as well as optical interconnection networks. However, since the ANN can be implemented using optics, this routing approach is especially appealing for an optical computing environment. Although the ANN does not always generate the best solution, the parallel nature of the ANN computation may make this routing scheme faster than conventional routing approaches, especially for OMIN's that have an irregular structure. Furthermore, the ANN router is fault-tolerant. Results are shown for generating routes in a 16×16, 3-stage OMIN     

自由空间光互连洗牌型神经网络模型

首先介绍一种洗牌型自由空间光互连多层全互连神经网络模型。该模型的高神经元／权重比可以极大地压缩神经网络的互连权矩阵IWM（interconnectweightmatrix）。对于具有N2个神经元的单层二维全互连神经网络的IWM为N2×N2,而洗牌型全互连神经网络的IWM仅为4N2log2N。另外,洗牌型全互连神经网络整齐、简单的结构方便了网络的综合,特别是网络隐单元的综合,并且十分适合于神经网络的光学实现。然后描述了采用数字光技术实现光互连的洗牌型神经网络的系统模型、关键芯片结构以及关键技术。本文提出的模型和方法使实现与人脑神经网络规模（104量级）相当的实用化自适应光电子全互连神经网络成为可能。     

Interprovider differentiated service interconnection management models in the Internet bandwidth commodity markets

Due to the recent evolution of telecommunications infrastructure and the Internet as a commodity market for bandwidth, Internet Service Providers (ISPs) encounter new issues concerned with bandwidth management for the network interconnection. Bandwidth commodity exchange is considered a new B2B (Business-to-Business) electronic commerce application that brings new market opportunities to carriers and service providers for managing their bandwidth resources. This paper develops market-based bandwidth management optimization models for Differentiated Service (DiffServ) QoS (Quality of Service) networks using an implementation of the bandwidth management agent, BMP (Bandwidth Management Point). We use network economic models to formulate an optimization problem for the interconnection and resource allocation policy of the DiffServ network. We formulate and develop those economic models as optimization problems of LP, NLP, MILP and mixed integer nonlinear programming (MINLP), and discuss the pricing mechanisms and available solution approaches for the implementation of the BMP's resource optimization process. Different opportunity costs are estimated based on the results of a network simulation using traffic flow statistics measured from a recent Internet backbone. We then numerically simulate the behavior of backbone network ISPs to optimize their profits for various demand scenarios.     

VLSI considerations for TESH: a new hierarchical interconnectionnetwork for 3-D integration

This paper discusses very large scale integration (VLSI) issues, including reconfiguration and yield, for a new interconnection network, “Tori connected mESHes (TESH)”. Its key features are the following: (1) it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors, (2) it permits efficient VLSI/ULSI (ultralarge scale integration) realization, and (3) it appears to be well suited for three-dimensional (3-D) implementation. This is due in part to the fact that it requires far fewer number of vertical wires than most other multicomputer networks of comparable diameter, as demonstrated by a 4096 node example. Presented in the paper are the architecture of the new network, node addressing and message routing, VLSI considerations, and most importantly, the reconfiguration and yield studies     

Using the multistage cube network topology in parallelsupercomputers

A critical component of any large-scale parallel processing system is the interconnection network that provides a means for communication along the system's processors and memories. Attributes of the multistage cube topology that have made it an effective basis for interconnection networks and the subject of much ongoing research are reviewed. These attributes include O(N log₂N) cost for an N-input/output network, decentralized control, a variety of implementation options, good data-permuting capability to support single-instruction-stream/multiple-data-stream (SIMD) parallelism, good throughput to support multiple-instruction-stream/multiple-data-stream (MIMD) parallelism, and ability to be partitioned into independent subnetworks to support reconfigurable systems. Examples of existing systems that use multistage cube networks are considered. The multistage cube topology can be converted into a single-stage network by associating with each switch in the network a processor (and a memory). Properties of systems that use the multistage cube network in this way are examined     

Multistage shuffle networks with shortest path and deflectionrouting for high performance ATM switching: the open-loopshuffleout

A new class of switching architectures for broadband packet networks, called shuffleout, is described and analyzed in the paper. Shuffleout is basically an output-queued architecture with a multistage interconnection network built out of unbuffered b×2b switching elements. Its structure is such that the number of cells that can be concurrently switched from the inlets to each output queue equals the number of stages in the interconnection network. The switching element operates the cell self-routing adopting a shortest path algorithm which, in case of conflict for interstage links, is coupled with deflection routing. The paper presents the basic shuffleout architecture, called open-loop shuffleout, in which the cells that cross the whole interconnection network without entering the addressed output queues are lost. The key target of the proposed architecture is coupling the implementation feasibility of a self-routing switch with the desirable traffic performance typical of output queueing