Electronically tunable floating resistor

A new design for an electronically tunable floating resistor is proposed. The proposed circuit can be realized as a positive or negative resistor without changing the circuit topology, and can be tuned electronically. Simulation results are obtained to show adequate agreement with theory.     

FGMOS based tunable grounded resistor

This paper proposes a novel floating gate MOSFET (FGMOS) based tunable grounded resistor (FGTGR). The FGTGR has been implemented using a single 3-input FGMOS. In the drain current equation of 3-input FGMOS, the gate voltage is equal to the weighted-sum of the 3 input voltages, namely V _in (input voltage), V _C (control voltage), and V _b (bias voltage). The input gate voltage (V _in ) with appropriate conditions has been used to cancel the nonlinear-term present in the drain current equation of FGMOS operating in the ohmic region. The control voltage V _C has been used to control the resistor value and the bias voltage V _b has been used to realize either a threshold-dependent or a threshold-independent FGTGR. The FGTGR is simple, compact, accurate, and with low power dissipation of 1.63 μW. The workability of the FGTGR and the high pass filter realized by using the same, have been confirmed by SPICE simulations in 0.5 μm CMOS technology.     

Sub-threshold synchronizer

Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to interface between these sub-systems. However, VDD scaling rapidly degrades synchronizers' performance making them unsuitable for sub-threshold operation. For the first time, we analyze the synchronizer performance at ultra low voltages and propose to apply forward body bias to extend the operation of synchronizers to the sub-threshold region and to make them resilient to process variation. We show that applying full-VDD bias significantly increases the transconductance of the bi-stable in synchronizers without adding capacitance to the switching nodes. As a result all the circuit parameters (τ metastability time constant, T_d normal propagation delay and T_w metastability window) determining synchronizer performance or mean time between failure (MTBF) can be improved by more than 80% (i.e. by five times) in the sub-threshold region. We also study the impact of process variation on the synchronizer performance in the sub-threshold region and conclude that with full-VDD bias the synchronizer MTBF can be improved from seconds to years for the worst case corner. Finally, we propose an implementation scheme of full-VDD body-biased synchronizer, which is able to work for a wide range of VDDs from sub-threshold region to nominal VDD with nearly zero overhead.     

Improved de-embedding technique for polysilicon resistor modelling

In this article, accurate de-embedding technique based on transmission line theory is presented and applied to on-wafer polysilicon resistors fabricated in 130-nm SiGe technologies. Compared with the conventional de-embedding methods, not only the top metal layer, but also the under-layer metal parasitics are removed from the on-wafer passives. A systematic method relying exclusively on embedded S-parameters is used for the direct extraction of device circuit elements. This extracted method is characterised by its simplicity and ease of implementation. The proposed de-embedding technique and extraction approach are validated by polysilicon resistors with occupying areas of 20?×?2?µm². Good agreement between the measured and modelled data is obtained from 100?MHz up to 20.1?GHz.     

R-MOSFET structure based on current division

A parallel-path combination of resistors and MOSFETs is proposed for use in integrated continuous-time filters and other circuits. The technique allows continuous incremental tuning while maintaining significantly better linearity than MOSFET-only structures.<>     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.     

Electronical tunable millimeterwave oscillators in slotline technique

A new electronical tuning process is proposed for a millimeterwave oscillator in slotline-technique. The circuit used for the GaAs-FET oscillator is realized by a slotline coupler-structure in which the feedback between the resonator and the transistor drain is made by help of electromagnetical field.     

CMOS亚阈型带隙电压基准的分析与设计

带隙基准可提供近似零温度系数和大的电源电压抑制比的稳定电压基准,且与工艺基本无关。文中分析了M O SFET工作于强反型区与亚阈区的电压和电流限定条件,结合自偏置电路结构,给出了一种基于亚阈区的低功耗CM O S带隙基准电路的设计。     

一种亚阈型自举带隙基准电压源的设计

采用TSMC0．35μm CMOS工艺,基于对传统带隙基准电路的分析,利用MOS管的亚阈特性,设计了一种低压低功耗的带自举的带隙基准电压源。最后的HSPICE仿真结果表明了该电路具有较低的工作电压,较低的功耗和较低的温度系数。     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一。随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈。该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性;然后,采用INWE最小宽度尺寸与分指版图设计方法,提高电路的开关阈值与MOS管的驱动电流;最后,在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库,完成测试验证。实验结果表明,所设计的亚阈值标准单元与文献相比,功耗降低7.2%～15.6%,噪声容限提升11.5%～15.3%,ISCAS测试电路的平均功耗降低15.8%。     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一.随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈.该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案.该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性;然后,采用INWE最小宽度尺寸与分指版图设计方法,提高电路的开关阈值与MOS管的驱动电流;最后,在TSMC?65?nm工艺下构建标准单元的物理库、逻辑库和时序库,完成测试验证.实验结果表明,所设计的亚阈值标准单元与文献相比,功耗降低7.2％～15.6％,噪声容限提升11.5％～15.3％,ISCAS测试电路的平均功耗降低15.8％.     

基于亚阈值电流阵列的低成本物理不可克隆电路设计

物理不可克隆函数(PUF)能够提取出集成电路在加工过程中的工艺误差并将其转化为安全认证的密钥。由于常用于资源及功耗都受限的场合,实用化的PUF电路需要极高的硬件利用效率及较强的抗攻击性能。该文提出一种基于亚阈值电流阵列放电方案的低成本PUF电路设计方案。亚阈值电流阵列的电流具有极高的非线性特点,通过引入栅控开关和交叉耦合的结构,能够显著提升PUF电路的唯一性和稳定性。此外,通过引入亚阈值电流的设计可以极大地提高PUF的安全性,降低传统攻击手段的建模攻击。为了提升芯片的资源利用率,通过详细紧凑的版图设计和优化,该文提出的PUF单元面积仅为377.4 μm²,使得其特别适合物联网等低功耗低成本应用场景。仿真结果表明,该文所提亚阈值电路放电阵列PUF具有良好的唯一性和稳定性,无需校准电路的标准温度电压下唯一性为48.85%;在温度范围–20～80°C,电压变动范围为0.9～1.3V情况下,其可靠性达到了99.47%。     

The tunnel resistor

Nonlinear load resistors in high-speed tunnel-diode computer circuits offer several advantages over conventional linear load resistors, namely reduced power dissipation and therefore higher packing density, increased switching speed and relaxed tolerances on the power supplies. Such resistors have been constructed by combining a tunnel-diode junction with tunneling leakage paths on the surface of the same semiconductor junction using a metal plating technique. The plated metal, which on the average is less than monoatomically thin, forms conducting islands through which tunneling takes place in parallel with the tunneling across the junction. The added conductance is in itself nonlinear. The resulting characteristic exhibits a plateau where the current is substantially independent of voltage over a range of 50-100mv. The parallel resistance applied in this manner is free of the spurious reactances usually connected with resistances applied outside or on the surface of the encapsulation of the tunnel diode, and therefore allows stable operation up to very high frequencies. At the same time the application method allows the necessary very close control of the characteristics of the resulting combination. Results are presented using Ge, GaAs and Ga Sb and include information on radiation tolerance and life tests.     

PVT恒定高精度亚阈值CMOS电压基准源

提出一种基于SMIC 65 nm标准CMOS工艺库的高精度电压参考源电路。对3种不同类型偏置于亚阈值区的NMOSFET进行了讨论,采用无电阻温度补偿对温度进行高阶补偿,可以减小对工艺、电压、温度的敏感性。仿真结果表明:在不同工艺角下,电源电压、温度使基准电压Vref的变化仅为±1.36%。电压参考源的温度系数大约为4.5×10-6℃-1,电源线性调制率为2.1%m V·V-1,最小工作电压仅为0.56 V。     

DC feedback technique for temperature stabilisation of tunable CMOS transconductors

A simple technique for stabilising the transconductance of CMOS transconductors against temperature variations, with no need of external frequency reference signals, is presented. Accurate electrical simulations demonstrated that a 2.6% maximum transconductance variation over the temperature range -55-150/spl deg/C and a 600% tuning range can be obtained.     

一种低压CMOS亚阈型PTAT基准源

设计了一款工作在低电源电压且与绝对温度成正比(PTAT)的基准电路;采用衬底偏置技术、电阻分压作为PMOS放大器的输入和用工作在亚阈值区的NMOS管代替衬底PNP管三种方法,使得该电路可以在低电源电压下工作,且工作电流较小。该电路采用CSMC 0.6μm2P2 M工艺,电源电压为1.2 V、温度为0~100℃时,输出电压的温度系数为0.912 mV/K,电源电流为6.8μA;当电源电压在1.1~2.0 V变化时,室温下的输出电压是461.4±0.4 mV。     

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

This paper reported the sub-threshold behavior of long channel undoped surrounding-gate (SRG) MOSFETs with respect to body radius. Based on a rigorous channel potential model presented in this work, the ideal room temperature subthreshold slope of 60 mV/dec can only be achieved when the silicon body radius is smaller than a critical value. With larger silicon body radius, SRG MOSFETs display a dual subthreshold slope of 60 mV/dec and 120 mV/dec. Based on the complex subthreshold characteristics, a new definition of threshold voltage together with an extraction method is adopted to investigate threshold voltage characteristics of undoped SRG MOSFETs in this paper.     

用接地电阻器调谐振荡器

为了改变任何正弦波振荡器的频率,你应使用一对同轴可变电阻器,并且应该在整个变化范围内完全匹配其特性以满足振荡器平衡条件.这一制约条件导致调谐范围的种种问题及成本提高,从而限制了其应用范围.图1所示的正弦波振荡器不存在上述缺点.仅仅使用可变电阻器R,就可以在很宽的频率范围内对它进行调谐.该振荡器无需进行平衡,所以不存在匹配问题.     

Frequency stabilization of tunable DBR laser using multiwavelengthlight injection locking technique

This paper proposes a frequency stabilization scheme for tunable three-section DBR laser diodes (3S-DBR LD) that use multiwavelength light injection locking. The oscillating wavelength of the SS-DBR LD is discretely switched between cavity modes when the injection current into DBR section is changed, and locked to one wavelength of the multiwavelength light injected from the DBR section facet under the injection locking condition. The light injection properties of the capture range and the relationships of relaxation oscillation versus input power and detuning are investigated experimentally. Injection locking on the multistate wavelength of a tunable DBR LD is performed using a two wavelength multiplexed light. As a result, we demonstrate 1 GHz capture range and more than 26 dB rejection ratio for the multiplexed injected light     

巨磁电阻传感器

利用材料的巨磁电阻 (GMR)效应 ,可制得新一类磁电阻传感器—— GMR传感器。与传统的磁阻传感器相比 ,GMR传感器具有灵敏度高、可靠性好、测量范围宽、抗恶劣环境、体积小等优点 ,有广泛的应用前景。本文就目前已商业化的几种 GMR传感器的工作原理作一评述