Nucleation, growth and retrogrowth of oxidation induced stacking faults in thin silicon-on-insulator

The nucleation, growth, and retrogrowth of stacking faults were investigated for thermally oxidized silicon-on-insulator substrates formed by the separation by implanted oxygen (SIMOX) method. It has been observed that for high oxidation temperatures (T >1150°C) oxidation induced stacking faults (OISFs) undergo a retrogrowth (shrinkage) process at noticeably lower temperatures than in bulk silicon. The retrogrowth process in thin film SIMOX substrates starts at approximately 1190°C for the 2 h thermal oxidations. In this paper, a model for the retrogrowth process is proposed based on the assumption that at high oxidation temperatures vacancies may be injected from the thermal oxide/top silicon interface. We suggest that the vacancy injection reduces the self-interstitial supersaturation and as a direct consequence, attenuates the OISF growth. We also propose that the self-interstitial supersaturation is reduced through point defect recombination inside the silicon overlayer and at the top-silicon/buried-oxide interface where a high density of steps and kink sites are found.     

Reverse current instabilities in amorphous silicon Schottky diodes:modeling and experiments

A new model for high bias transport is reported which describes the time-dependent reverse current variations in amorphous silicon Schottky diodes. This phenomenon is of practical importance in the design and optimization of pixels for large-area optical and X-ray imaging. In the model, the main components of the reverse current, namely thermionic emission and tunneling, are both affected by the electric field at the metal/amorphous silicon interface. Time-dependent variations in this electric field arise due to the release of charges trapped in defect states in the depletion region and to charge trapping at the interface. This effect is analyzed using the approximation that the tunneling component of the current is equivalent to a lowering of the potential barrier at the interface. The calculated time-dependent reverse current is compared with the measured data     

Physical origin of long-term charge loss in floating-gate EPROMwith an interpoly oxide-nitride-oxide stacked dielectric

The long-term charge loss characteristic in a floating-gate EPROM cell with an oxide-nitride-oxide (ONO) interpoly stacked dielectric has been studied quantitatively. It is found that trapped electrons at the nitride-oxide interface can directly tunnel through a thin ~30-Å top oxide. The estimated tunneling barrier height is about 2.6 eV, which is consistent with the previous result based on MNOS studies. The thermal activation of the long-term charge loss is believed to be caused by the availability of trapped electrons at the top oxide-nitride interface. The thermal activation energy of the long-term charge loss is about 0.37 eV, which is similar to the activation energy of the second phase. It is believed that the trapped electron density at the top oxide-nitride interface becomes larger at higher temperatures due to the activated electron movement during the second phase     

Multiphonon capture of charge carriers by deep-level centers in a depletion region of a semiconductor

Multiphonon field-assisted thermal capture of thermally equilibrium charge carriers by deep-level centers located in a depletion region of a semiconductor is analyzed. It is shown that, in the case of strong electron-phonon coupling (SEPC), the multiphonon capture with preliminary tunneling of an electron through a potential barrier in the depletion region occurs with a lower rate as compared to the direct multiphonon capture in the electrically neutral bulk of the semiconductor, whereas, in the case of weak electron-phonon coupling (WEPC), the capture rate in the depletion region of a semiconductor may exceed that in the electrically neutral bulk by several orders of magnitude. The results of experimental study of capture processes in AlGaAs doped with silicon indicate that electron-phonon coupling is strong in DX centers.     

Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

Potentials and direct current in Si-(20 to 40 Å)SiO2-metal structures

The effects of oxide thickness and interface states on potentials in and direct currents through MOS structures with various metal contacts on 20–40 Å thick SiO₂ films and nondegenerate Si were investigated using a recently developed method of determining surface potential vs. bias and interface state vs. energy distributions of such structures from conventional admittance measurements. For Cr, Cu, and Mg contacts, the interface states are predominantly of acceptor type. The metal silicon work function differences are φ_MS = 0.91 V for Au, −0.04 for Cr, 0.18 for Cu, and −1.07 V for Mg. The forward device current consists mainly of majority carriers emitted over the Si barrier and tunneling through the oxide into the metal for depletion or weak inversion of Si, and of majority carriers tunneling from Si through the oxide into the metal for Si accumulation. Excess currents in forward and reverse direction are caused by carrier generation-recombination in interface states and tunneling through the oxide to and from the metal. The drooping of the forward current, deviating strongly from an ideal exponential characteristic, is mainly caused by the drop of a considerable part of the applied bias across the oxide layer.     

A model of electrical conduction in polycrystalline silicon

This paper presents a modified version of the conduction model for polycrystalline silicon which includes the thermionic field emission of carriers through the space-charge potential barrier, carrier tunneling through the grain-boundary rectangular potential barrier after being thermally emitted over the space-charge barriers, and the thermionic emission of carriers over these barriers. It is found that if the height of the space-charge potential barrier is much smaller than the height of the grain-boundary barrier, the conduction is mainly controlled by the second mechanism. As grain size decreases, the contribution to current by second mechanism increases. The model predicts that the grain-boundary width in phosphorus-doped polycrystalline silicon film is a strong function of dopant concentration at intermediate dopant concentrations, while the grain-boundary width in boron-doped polycrystalline silicon is independent of dopant concentration in the range of 10¹⁶to 5 × 10¹⁹cm^-3. Considering the potential drop across the grain-boundary barriers, the computed variation of resistivity with dopant concentration for different grain sizes is found to agree with the available experimental data.     

The mechanism of metal conductivity over the interface between organic insulators

The hopping mobility of charge carriers (both at the surface and in the bulk) is analyzed theoretically in the presence of electron–hole pairs. A physical model is suggested for the metal conductivity over the interface between organic materials, each being an insulator by itself. The conductivity is due to the rather high surface density of geminate pairs formed at the interface. Conditions are established wherein the transitions of a significant portion of charge carriers between molecules do not require thermal activation or tunneling. The surface conductivity and mobility of charge carriers are estimated by numerical simulation.     

Field dependence of the capture and re-emission of charge carriers by shallow levels in germanium and silicon

The capture and re-emission of charge carriers by shallow traps in lithium-compensated samples of gallium-doped germanium and boron-doped silicon have been studied by a transient charge drift method. The field dependence of the capture coefficient for hot carriers was observed at low temperatures and high electric fields; capture coefficients of the order of 10^?6 to 10^?7 cm³ sec^?1 were found. The re-emission of the trapped carriers was strongly affected by the electric field. This effect is well explained by a lowering of the Coulomb potential barrier about the trapping centres (the Poole-Frenkel effect) which enhances thermal re-emission. At the highest fields and lowest temperatures, the re-emission from the shallow traps in germanium appeared to be dominated by tunnelling.     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

Some observations on charge buildup and release in silicon dioxide irradiated with low energy electrons

The positive charge buildup produced in silicon dioxide by low energy electrons (0 to 30 keV) has been investigated as a function of beam energy and oxide thickness. The induced charge, as evidenced by displacement of capacitance versus voltage plots, was found to be a function of the beam energy dissipated within the oxide in the vicinity of the oxide-silicon interface. The charge induced at a particular fluence level in an oxide of given thickness increases with energy up to some level Emaxbeyond which the charge buildup rate falls off as the energy is increased further. Continued falloff in the buildup rate was observed in several samples irradiated at energies of 200 keV and 1 MeV. Emaxhas been found to correspond to the beam energy which, according to predicted range-energy data, produces maximum energy dissipation per unit path length in the oxide near the silicon interface. Constant temperature annealing of irradiated MOS samples has indicated that the annealed charge is linearly dependent on the logarithm of elapsed time over a finite time interval. This is particularly evident at room temperature where a linear dependence on In (t) has been observed out to 10⁵seconds. Such a time dependence of released charge can result either from thermal activation of trapped carriers from a uniform trap distribution or from thermal emission of recombination electrons over a Schottky barrier from the silicon into the oxide; however, both of these models predict the released charge to be a linear function of absolute temperature. A much stronger temperature dependence has been observed during these experiments.     

Study of the positive charge buildup into buried oxide of SIMOX SOI structure during bias–temperature stress

The buildup of fixed and mobile charge in the buried oxide (BOX) of silicon implanted by oxygen (SIMOX) silicon-on-insulator (SOI) structures during bias–temperature (BT) cycling has been studied by the thermally stimulated polarization (TSP) current technique and C–V measurements. Two polarization processes have been observed: the first process with activation energy of 0.3 eV is likely related to the positively charged ion transport across the BOX, the second process with activation energy about 1.2 eV is associated with space charge polarization. It was found that the ion transport is created simultaneously with the process of lateral positive charge buildup near the BOX/substrate interface when the bias is applied to the structure at temperatures above 280°C.     

Experimental characterization of electron-hole generation in silicon carbide

Thermal generation in wide bandgap semiconductors can be observed by monitoring the capacitance recovery transients of npn (or pnp) storage capacitors in which the middle layer is floating. In this article, we report a study of thermal generation in 4H and 6H silicon carbide (SiC). Three generation mechanisms are identified: bulk generation in the depletion regions of the pn junctions, surface generation at the periphery of the capacitors, and defect generation associated with imperfections in the material. All three generation mechanisms are thermally activated. Bulk generation and surface generation have activation energies of approximately half bandgap, while defect generation exhibits field-induced barrier lowering resulting in an apparent activation energy less than half bandgap. Because the generation rate is extremely low, most measurements are conducted at elevated temperatures (250-350°C). However, we also describe a long-term measurement at room temperature in which the 1/e recovery time appears to be in excess of 100 years.     

The barrier height change and current transport phenomena with the presence of interfacial layer in MIS Schottky barrier solar cells

In this comprehensive study, several interesting results which are different from those previous are reported. We find the barrier height decreases for n-type and increases for p-type when positive ions are introduced into the insulating layer. The increase of open circuit voltage can be traced to the suppression of the dark saturation current by the depletion field induced by the positive charge, and to the diminution of the majority tunneling current by the oxide potential barrier. The tunneling probabilities for majority and minority carriers are different; there are only a finite amount of majority carriers with thermionic energy greater than q(V_bi ? V_s) which can surmount the depletion potential and tunnel into the metal, whereas the photogenerated minority carriers derive kinetic energy in the depletion layer making tunneling easier. Transport coefficients for electrons to transmit from metal to semiconductor and from semiconductor to metal are different for the departure of built in potentials during illumination.     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

Tunnel-recombination currents and electroluminescence efficiency in InGaN/GaN LEDs

The mechanism of injection loss in p-GaN/InGaN/n-GaN quantum-well LEDs is analyzed by studying the temperature and current dependences of external quantum efficiency in the temperature range 77–300 K and by measuring transient currents. The data obtained are interpreted in terms of a tunnel-recombination model of excess current, which involves electron tunneling through the potential barrier in n-GaN and the over-barrier thermal activation of holes in p-GaN. At a low forward bias, the dominant process is electron capture on the InGaN/p-GaN interface states. At a higher bias, the excess current sharply increases due to an increase in the density of holes on the InGaN/p-GaN interface and their recombination with the trapped electrons. The injection of carriers into the quantum well is limited by the tunnel-recombination current, which results in a decrease in efficiency at high current densities and low temperatures. The pinning of the Fermi level is attributed to the decoration of heterointerfaces, grain boundaries, and dislocations by impurity complexes.     

Formation of thermal donors in SIMOX material

Thermal oxygen donor generation in SIMOX material formed in Czochralski (CZ) and oxygen free float zone (FZ) silicon was investigated by Hall and photoluminescence techniques. It was determined that residual interstitial oxygen was introduced to silicon by the SIMOX buried oxide formation process thus increasing the possibility of thermal donor creation. Significantly, thermal donor generation was identified and localized to the top silicon region in FZ material. The detected concentration of residual oxygen was on the order of 5 × 10¹³ cm^-3 and is negligible when compared to the intrinsic oxygen concentration of the starting CZ bulk material.     

Tunneling through ultrathin GaAs n++-p++-n++ barrier grown by molecular layer epitaxy

The I-V characteristics of ultrathin GaAs n⁺⁺-p⁺⁺ -n⁺⁺ barrier structures with a 45 Å thick p⁺⁺ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices     

The effect of 1300-1380°C anneal temperatures and materialcontamination on the characteristics of CMOS/SIMOX devices

The characteristics of CMOS transistors fabrication on silicon implanted with oxygen (SIMOX) materials were measured as a function of the silicon superficial layer contamination levels. In addition, postimplant anneal temperatures of 1300°C, 1350°C, and 1380°C were examined. It is found that the transistor leakage currents as well as the integrity of the gate oxide and implanted SIMOX oxide are functions of the carbon content in the starting material. Leakage currents below 1.0×10^-12 A/μm of channel width have been measured when the carbon concentration is reduced to 2×10¹⁸/cm². In addition, the integrity of the transistor gate dielectric, SIMOX implanted oxide, and oxygen precipitate density are seen to be a function of the postimplant anneal temperature. A gate dielectric breakdown field of 10 MV/cm has been achieved when the postimplant temperature is increased to 1380°C     

Current-voltage characteristics of high current density siliconEsaki diodes grown by molecular beam epitaxy and the influence ofthermal annealing

We present the characteristics of uniformly doped silicon Esaki tunnel diodes grown by low temperature molecular beam epitaxy (T_growth=275°C) using in situ boron and phosphorus doping. The effects of ex situ thermal annealing are presented for temperatures between 640 and 800°C. A maximum peak to valley current ratio (PVCR) of 1.47 was obtained at the optimum annealing temperature of 680°C for 1 min. Peak and valley (excess) currents decreased more than two orders of magnitude as annealing temperatures and times were increased with rates empirically determined to have thermal activation energies of 2.2 and 2.4 eV respectively. The decrease in current density is attributed to widening of the tunneling barrier due to the diffusion of phosphorus and boron. A peak current density of 47 kA/cm² (PVCR=1.3) was achieved and is the highest reported current density for a Si-based Esaki diode (grown by either epitaxy or by alloying). The temperature dependence of the current voltage characteristics of a Si Esaki diode in the range from 4.2 to 325 K indicated that both the peak current and the excess current are dominated by quantum mechanical tunneling rather than by recombination. The temperature dependence of the peak and valley currents is due to the band gap dependence of the tunneling probability