一种开环高速高精度采样保持电路

设计了一种改进型开环结构采样保持电路.与传统Miller电容开环结构相比,本设计采用了新型Bootstrapped开关,不但实现了沟道导通电阻线性化,而且消除了与输入信号相关的时钟馈通;采用全差分结构消除了共模信号引入的误差以及偶阶谐波,提高了电路的信噪比;采用高速高精度缓冲器增大电路的驱动能力,实现了高速高精度采样.设计采用0.35μm n-well CMOS工艺,经仿真验证,在驱动2.5pF负载电容下采样率达到100MSPS,电路有效位数12bits,功耗为21.5mW.     

一款0.16 mm2基于180 nm CMOS采用全局去偏斜的半速率8×2.5 Gb/s时钟转发架构接收机

在时钟转发架构的高速有线通信接收机中,需要去偏斜电路实现时钟与数据之间的最佳采样关系,并保证多路数据的同步。本文提出了一种全局去偏斜方案,仅采用一路数据与时钟进行对齐,并通过时钟延时匹配与分布技术实现多路数据同步,减小了各通道独立去偏斜方案带来的功耗与面积开销。所提出的接收机由8路数据通道、1路半速率转发时钟通道与基于延迟锁定环路的全局去偏斜电路构成。基于180 nm CMOS工艺,在2.5 Gb/s数据率下,可去除输入时钟与数据任意偏斜,得到位于数据中心的采样相位,同时具有时钟占空比校准能力。在1.8 V电源电压下,所提出的接收机总功耗为187 mW,总面积为0.16 mm²,对比各通道独立去偏斜方案,功耗和面积开销分别节约了45.2%与62.8%。     

超高速CMOS动态负载分频器设计及研究

在比较反转触发器(TFF)的各种结构的基础上,给出了一种单时钟信号控制实现超高速分频的电路结构,以及具体设计过程.分频器使用动态负载,输出两路互补信号.采用SMIC 0.18um IP6M CMOS工艺,在电源电压为1.8 V的情况下,仿真实现了工作速度10 GHz(可工作频率范围为1-13.5 GHz)、功耗仅为3.1 mW的二分频器,可用于超高速锁相环、时钟数据恢复设计中.     

应用于高速数据采集系统的超低抖动时钟电路

分析了高速数据采集系统对采样时钟抖动的要求，给出了时钟相位噪声和时钟抖动的转换关系；采用HITTITE的HMC1035LP6GE频率综合芯片作为主芯片，设计了时钟生成电路，2 500 MHz输出时钟抖动测量值90 fs（整数工作模式，输入频率100 MHz，鉴相频率100 MHz，环路滤波带宽127 kHz，积分区间［10 kHz，10 MHz］）。对比时钟生成电路在各种工作模式下的性能，给出了对应的设计指南。     

基于 AD73360和TMS320F2812 的数据采集系统设计

多输入通道之间的相位误差是数据采集系统的重要问题之一。采用六输入通道模数转换器件AD73360和数字信号处理器TMS320F2812设计了多通道数据采集系统,实现了两者之间的接口电路和通信程序设计。该系统可用于多路输入信号的同步采样,实验证明了系统的有效性。     

用于高速传感器的宽频差分50％占空比校正器

提出了一种用于高速传感器的宽带差分50％占空比校准电路。与传统CMOS模拟占空比校准电路相比,所提出电路结构简单工作稳定,并且证明了该电路的最高校正频率可达4GHz。所提出电路中的占空比检测器采用基于低通预滤波的连续时间积分器和带有源耦合逻辑结构的时钟缓冲器链。采用了0.18μmCMOS工艺,并针对高速应用条件进行了优化。实验结果表明,所提出电路在500MHz至4.0GHz频率范围内正常,可接受的输入占空比为30％?70％。在4GHz输入信号条件下功耗为5.37mW,输出抖动为19.3ps。测试芯片面积为550μm×370μm。     

一种采样率为20兆赫每次采样10比特的A/D转换器

一种具有很高比特率的A/D转换器已经研制成功。其工作方式为串-并联型式,并且末级的输入相当于交流耦合。这一点是被输入信号的统计特性所允许的。该A/D转换器的样机具有下列性能:1)直流耦合模拟输入——能接收几乎所有的模拟信号以及电视信号;2)采样频率高达20兆赫;3)具有每次采样10比特的线性编码电路;4)线性误差小于量化电平的1/3;5)微分增益和微分相位分别为0.4%和0.25°;6)工作温度范围为0°～50℃。     

全数字化PET系统时间信号基准模块设计

为了满足为全数字化PET（正电子发射断层扫描仪）系统中前端电子学模块提供时间信号基准的时钟信号的要求,采用FPGA和AD9516-4芯片设计了一种时间信号基准模块。针对时间信号基准的要求,提出了通过参考基准频率由锁相环产生高频信号,同时利用分频器实现了对高频时钟信号的分频,并用LVDS（低电压差分信号）模式对生成的多路时钟信号进行输出,从而获得了多路频率、相位、幅值均相同的同步时钟信号的方法。相比于其他方法实现的时钟分配模块,本方法具有高精确度,低功耗和高稳定性的特点。该模块已经在全数字化PET系统中使用,验证了该模块具有高精确度和高稳定性的特点。     

基于4通道时间交织的FPGA高速采样系统

时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。     

一种宽带高性能TIADC时钟发生器

针对并行交替模拟数字转换器(TIADC)发展遇到的时钟瓶颈,提出了一种宽带高性能TIADC时钟发生器设计方案.该方案利用时钟分路器和可编程延迟器分别实现通道扩展和相位延迟,采用可配置时钟源和逻辑转换电路使时钟发生器能够输出低抖动的CMOS和ECL逻辑TIADC时钟.设计实现的时钟发生嚣已经成功用于4通道12 bit 320 MHz采样率的TIADC系统.测试结果表明,该时钟发生器具有10 ps延迟偏差和在80MHz频率下不超过2 ps的时钟抖动.     

Arbitrary terminated negative group delay circuit using signal interference concept

In this article, we demonstrate signal interference concept based wideband negative group delay (NGD) circuit with an arbitrary termination port impedance. The proposed circuit consists of unequal power division ratio 180° hybrid and in‐phase combiner. The NGD can be generated by controlling power division ratios of 180° hybrid and combiner. For experimental verification, the circuit is designed and fabricated at a center frequency of 2 GHz. The experiment results show that the proposed NGD circuit can provide 460 MHz NGD bandwidth (bandwidth of group delay <0 ns) with group delay of ?0.8 ns at 2 GHz.     

A 10 GHz multiphase LC VCO with a ring capacitive coupling structure

A multiphase LC voltage-controlled oscillator(VCO) with a novel capacitive coupling CL ladder filter structure is proposed in this paper and this 10 GHz eight-phase VCO is applied in clock and data recovery(CDR) circuit for 40 Gb/s optical communications system.Compared with the traditional eight-phase oscillator,this capacitive coupling structure can decrease the number of inductors to half and only of four inductors.The VCO is designed and taped out in TSMC 65 nm CMOS technology.Measurement results show the phase noise is 105.95 dBc/Hz at 1MHz offset from a carrier frequency of 10 GHz.The chip area of VCO is 480 μm×700 μm and the VCO core power dissipation is 4.8 mW with the 1.0 V supply voltage.     

A multiband carrier generation architecture for UHF, 2.4 GHz,and 5 GHz ISM applications

Novel multiband carrier generation architecture is proposed that can be applicable for RFID reader, WLAN 802.11a‐b‐g, and ZigBee sensor network, and implemented with 0.18 μm CMOS technology. In the proposed architecture, a quadrature voltage controlled oscillator (QVCO) is implemented by coupling two differential cross‐coupled LC VCOs to generate in‐phase (I) and quadrature (Q) signals operating at one‐thirds of the 5 GHz frequency range. As well, the differential second harmonic signal of the VCO core frequency is generated by mixers, and then converted to I/Q signals via a single‐stage tunable polyphase filter. By single sideband mixing of the I/Q signals of the QVCO and the polyphase filter, a cleaner carrier signal can be generated in the frequency band of 5 GHz. By including extra frequency dividers, the architecture can also be reconfigured to generate UHF band and 2.4 GHz band. The proposed architecture draws about 32 mA including the QVCO core current consumption of 2.8 mA from 1.8 V supply. The measured tuning frequency of the QVCO core ranges from 1.57 to 1.84 GHz. The measured phase noise is ?104.5 dBc/Hz at 1 MHz offset from 4.84 GHz. The chip layout occupies an area of 1.44 × 1.4 mm² on Si substrate, including the DC and RF pads. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

一种用于高能离子注入机射频加速的数字移相器设计

设计了一种基于STM32F405RGT6微处理器和AD9959的高能离子注入机射频加速用数字移相器,首先介绍了移相器的系统组成和工作原理及如何实现高能离子注入机多腔射频加速系统中射频电源的相位控制,然后对微处理器、DDS芯片AD9959、时钟分配芯片AD9510等硬件电路原理和控制软件设计作了详细的介绍;实验结果表明该移相器实现了16通道正弦信号输出,输出波形频率和相位值分辨率分别高达0.02Hz和0.05°,可以完成任意两路之间的相位差调节和设置。该移相器结构简单,性能稳定可靠,能够满足高能离子注入机多腔射频加速系统中射频电源的相位控制要求。     

基于去抖缓冲区的快速自适应时钟方法

分析了分组网传送TDM技术中的自适应时钟方法,描述现有的基于去抖缓冲区填充级的自适应时钟方法,提出一种基于去抖缓冲区的快速锁定的自适应时钟方法,比较快速锁定方法和传统的基于填充级方法,设计和建立硬件设备和评测平台。测试表明了该改进算法的有效性。     

神经网络正弦信号发生器

针对正弦信号发生器设计中，直接数字频率合成技术存在相位截断误差的问题，以神经网络为技术基础，以FPGA为硬件核心，提出了一种新型的高频正弦信号发生器设计方案，有效克服了上述问题。阐述了这种方案的工作原理、电路结构以及设计思路和方法。经过设计和仿真测试，系统的主时钟频率可以达到95 MHz且不占用ROM存储空间，输出的正弦信号为2.5 MHz时，输出信号的杂散抑制为80 dB，可见该方案资源占用率低，无相位截断，输出信号杂散小且输出频率较高。     

IEEE1588协议硬件时间戳标记电路设计

IEEE1588协议是一种基于网络多播技术的精密时钟同步协议,为了提高时钟同步的精度,提出了一种在以太网物理层和MAC层之间的介质无关接口(MII/RMII)处检测同步报文的策略和实现精确时间戳标记方案,在此方案基础上设计和实现了基于FP-GA的硬件时间戳标记电路;设计了相关测试平台,对设计电路进行了测试和验证,测试结果表明设计的时间戳标记电路可以在RMII接口处实时地标记同步报文的收发时间戳,设计达到课题要求,应用性能良好。     

Signal-integrity improvement method and its robustness evaluation for VLSI and VLSI-packaging

Nowadays, a GHz frequency signal needs to be propagated on a printed circuit board (PCB) with low distortions. In addition, a higher-frequency signal of 10 GHz or more will also need to be propagated with low distortion in very-large-scale integration (VLSI) in the future. However, signal propagation with low distortion is getting more and more difficult as the frequency increases. In order to solve this problem and to ensure signal integrity, we have proposed a novel transmission line called a “segmental transmission line” (STL). In the STL, a transmission line is divided into multiple segments of individual characteristic impedance. The multiple segments are designed to fix the waveform distortion on the transmission line by solving a combinatorial explosion problem using a genetic algorithm. In a previous article, we have shown the effectiveness of an STL designed for a GHz clock signal in computer simulations. We have also fabricated two scaled-up STL prototypes for a clock signal using real printed circuit boards (PCBs). In this article, we input a random signal by changing its frequency to the scaled-up STL prototype designed for a 150-MHz clock signal. We show that the STL has high robustness to the random signals and the frequency fluctuations, which indicates the generality of the STL technique.     

前馈环形振荡器的结构与相位噪声研究

基于高速串行通信系统中锁相环和时钟数据恢复电路的需求,研究了前馈环形振荡器的结构与工作原理;在传统结构的基础上,将前馈路径耦合至主路径反相器的源极,可以提高输出信号的边沿速率;最后基于Hajimiri模型的脉冲灵敏度函数进行分析,提出的结构有效降低了热噪声和闪烁噪声的引入.在28 nm CMOS工艺下设计了单源极前馈型...     

Reconfigurable frequency and steerable beam of monopole antenna based on graphene pads

This article presents a reconfigurable frequency and steerable beam monopole antenna based on tunable graphene pads operating in both 4G and 5G bands. The proposed antenna consists of printed CPW‐fed circular monopole shapes, with five rectangular strips added with a separation angle of 45°. These strips are connected to monopole by using graphene pads. The monopole antenna operates in the lower 5G band from 3 up to 7.8 GHz at ?6 dB reflection coefficient. The antenna has an omni‐radiation pattern over the operating band without any applied bias voltage to the graphene pads. By applying the DC bias voltage, the rectangular strips are connected to the monopole and the designed antenna start to resonate from 1.8 to 8 GHz adding the 4G band frequencies. The steering of the proposed antenna beam started from ?60° to 60° according to the bias of the connected graphene pads. The graphene pad exhibits a variable resistance realizing an almost short to an open circuit with and without voltage bias, respectively. The designed antenna is simulated using high frequency structure simulation (HFSS) Ansys ver. 19 and equivalent circuit model of the graphene. The antenna is fabricated using reduced graphene oxide (RGO) pads. Reflection coefficient and radiation pattern measurements as well as simulations are presented with a positive agreement between the results.