基于QUCS-S软件的共射极放大电路仿真

该文采用QUCS-S软件对多级放大电路进行仿真模拟。模拟过程中,在基本共射极放大电路中引入分压式电阻和电压串联式负反馈,可直接观察到其对整个电路动态指标造成的影响。仿真结果表明,引入了负反馈后的闭环系统与开环系统相比,其波形更加稳定,通频带宽度得到改善;引入分压式电阻的目的是稳定系统的静态工作点,模拟结果与理论结果一致。因此,通过计算机仿真可在实验前先行验证计算得出的结果,有效解决了实际操作中的烦琐性问题,同时也有利于学习者更好地掌握该部分内容。     

BOOST三电平直流变换器分压电容的均压方法

只有对分压电容进行有效的均压控制,才能够使Boost三电平直流变换器能够正常工作。本文分析了Boost三电平直流变换器的工作原理,指出了该变换器的两个分压电容分压不均的原因,并据此提出了一种均压的控制方法,它通过调整开关管的导通时间确保分压电容均压,最后利用PSIM结合控制算法对该变换器电路进行了仿真。论文最后给出了仿真结果来验证本方法的有效性。     

含负电容谐振分流电路的压电声子晶体梁的局域共振带隙与振动衰减

通过在树脂梁上周期贴敷压电片,并连接由被动电阻-电感(RL)谐振分流电路和负电容(NC)电路串联而成的分流电路,构造了压电声子晶体梁结构。采用传递矩阵法计算了该类型压电声子晶体梁结构的带隙特性,并对电阻、电感和负电容对局域共振带隙的影响进行了深入分析,发现分流电路中的LC电磁振荡回路可产生局域共振带隙,而串联的负电容电路则可增强压电片的机电耦合效率,从而增强带隙衰减范围和衰减幅值。采用振动实验方法对理论分析结果进行了验证,证实串联的负电容对局域共振带隙的增强作用,为局域共振声子晶体的设计提供了新的思路。     

本安电路电容放电模型与仿真分析

通过对电容实际放电电路的分析,建立了电容电路放电仿真模型和数学模型,利用MATLAB仿真出了在固定电容值下,串联电阻-放电能量及端电压-放电能量的关系曲线,从曲线中可查询到在特定条件下电阻与放电能量、端电压与放电能量的数值对应关系,并且通过了IEC火花试验装置火花点燃试验的验证.结果表明,曲线中高于放电能量阈值525μJ的电路发生了点燃,相反则未点燃,仿真模型评价结果与火花点燃试验结果一致,当设计电容电路中的等效电容值不在标准范围内或者没有专用的本安电路火花试验装置进行验证时,可以利用该方法进行模拟仿真,通过查询曲线与放电能量阈值进行比较来评定所设计电路的本安防爆性能.     

用于变频噪声吸收的压电声学超材料

提出基于压电声学超材料的吸声单元结构和电路，通过调节压电并联负阻抗电路实现吸声频率移动。吸声结构由质量块、压电层合板和刚性背板组成，压电并联电路包含负电容和负电阻电路。通过建立包含吸声结构声阻抗和电路阻抗的吸声系数分析模型，获得吸声频率与负电容的关系函数，并通过模型的稳定性分析确定吸声频率可调范围。单元样件的数值仿真和声管实验表明，负电容电路可将样件单元的吸声频率从1 130 Hz移动到910 Hz，负电阻电路可以补偿吸声系数到0.9以上。仿真与实验结果在可调频率范围内基本一致。     

负电容压电分流阻尼系统的能量耗散特性

在半主动压电分流阻尼技术中,采用不同结构负电容分支电路时,系统具有不同的阻尼特性.将负电容半主动分支网络分为串联电容/电阻支路、串联电容/电感/电阻支路、并联电容/电阻支路,获得了不同支路时系统的机械阻抗,比较分析了系统能量耗散因子及刚度比,发现串联电容/电感/电阻支路能获得更宽更高的中低频阻尼性能,而并联电容/电阻支路的高频阻尼性能较好.     

低功耗低相位噪声4.8GHz CMOS压控振荡器芯片设计

采用TSMC 0.18μm RF CMOS工艺设计并实现了一个应用于无线传感器网络射频前端频率综合器的低功耗、低相位噪声4.8GHz电感电容压控振荡器.此振荡器的核心电路采用电流源偏置的互补差分负阻结构,降低了电路对电源电压变化的灵敏度和功耗.电感电容谐振腔采用了降低相位噪声的设计方法.在不恶化相位噪声性能的前提下,核...     

低压CMOS压控振荡器设计

通过对LC压控振荡器原理的分析,设计了一种新型CMOS集成压控振荡器.该电路通过利用振荡器的输出产生高电压来控制开关电容阵列的开启来实现输出频率在不同频段中转换,从而提高输出频率范围和降低相位噪声.电路采用TsMc18rf工艺,用cadence的spectre工具进行仿真.结果表明:在0.6V的电源电压下,频率覆盖了2.07GHz到2.78GHz,可调控范围约为29%,总功耗约为1.8mw,1MHz频偏处相位噪声约为一120dB/Hz,满足了设计要求.     

电阻分压的10KV电子式电压互感器分析

基于电阻分压器的电子式电压互感器的原理、结构和输出信号等与传统的电压互感器有很大不同,其性能主要受电阻特性和杂散电容的影响。本文从等效电路的角度分析了电阻特性和杂散电容对电子式电压互感器测量准确度的影响;利用Ansoft软件包建立分压器的有限元模型对杂散电容进行了计算分析,并根据杂散电容分布对屏蔽罩进行了设计。在理论分析基础上,研制了一台电阻分压式的10KV电子式电压互感器,并进行了准确度测试。     

低频、低功耗CMOS LNA的设计优化技术

分析了具有源级退化电感的CMOS共源共栅结构电路在低频、低功耗LNA设计中存在的缺陷,为满足低频、低功耗设计的要求,现广泛采用在该电路结构基础上再并联栅极电容的结构.今按照噪声系数的定义严格推导了该结构电路的噪声参数表达式,并基于推导的公式分析了该结构在CMOS低频、低功耗LNA设计中的重要应用.最后实现了一个基于0.18μm CMOS工艺的ISM频段应用的433 MHz LNA的设计,运用Agilent公司的设计仿真软件ADS进行仿真,整个LNA的设计过程及ADS仿真结果与理论分析一致.     

Design and analysis of a phase modulator based on a metal-polymer-silicon hybrid plasmonic waveguide

A plasmonic-hybrid-waveguide-based optical phase modulator is proposed and analyzed. The field enhancement in the low-index high-nonlinear polymer layer provides nanoscale optical confinement and a fast optical modulation speed. At 2.5 V drive voltage, a π phase shift can be obtained for a 13-μm-long plasmonic waveguide. Because of its small capacitance and parasitic resistance, the modulation bandwidth can reach up to 100 GHz with a low power consumption of ～9 fJ/bit. The plasmonic waveguide is connected to a silicon wire waveguide via an adiabatic taper with a coupling efficiency of ～91%. The phase modulator can find potential applications in optical telecommunication and interconnects.     

Fabrication and radio frequency characterization of carbon nanotube field effect transistor: evidence of quantum capacitance

We fabricated an radio frequency (RF) carbon nanotube field effect transistor (CNTFET) whose electrode shapes were standard RF designed ground-signal-ground (GSG)-type pads. The S-parameters measured from our RF CNTFET in the frequency range up to 6 GHz were fitted with an RF equivalent circuit, and the extracted gate capacitance was shown to be the capacitance value of the series combination of the electrostatic capacitance and the quantum capacitance. The effect of the channel resistance and the kinetic inductance was also discussed.     

Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs

Accurate modeling and analytical parameter extraction of the non-quasi-static small-signal model of FinFETs are presented using a three-dimensional device simulator. Using simple Y- and Z-matrices calculations, the extrinsic gate-to-drain/source capacitance and source/drain resistance are de-embedded from the small-signal equivalent circuit. The analytical parameter extractions are performed by Y-parameter analysis after removing the extrinsic gate-to-drain/source capacitance and source/drain resistance. Accuracy of the model and extraction method is verified with the device-simulation data up to 700 GHz. Without any complex fitting and optimization steps, the total modeling rms error of the Y-parameter up to 700 GHz was calculated to be only 1.9 % in the saturation region and 2.1 % in the linear region. Also, the bias dependencies of the small-signal parameters are presented.     

A Josephson analog limiter circuit

The authors have designed, fabricated and successfully tested a Josephson integrated circuit that is used to limit the range of an analog input signal. The circuit consists of a single Josephson junction with a suppressed critical current. The impedance of this suppressed junction consists of the nonlinear quasiparticle resistance in parallel with the capacitance of the junction. The junction capacitance is used to advantage as one pole of a second-order low-pass filter, the other element of which is a thin-film inductor. This filter can perform the function of a slew-rate-limiting filter, at the input to a high-speed comparator. The authors fabricated individual junctions and measured their suppression characteristics and have found that a 2-μm×4.5 μm junction with a nominal critical current of 170 μA can be suppressed to less than 4 μA of critical current with a 14-mA control current. Complete limiter circuits have been fabricated and tested for both their DC and transient characteristics. Measured DC response is in good agreement with simulation, but parasitic capacitance present in the fabricated devices limited the -3 dB bandwidth to about 3.6 GHz     

Noise-tolerant quantum MOS circuits using resonant tunneling devices

Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.     

Thin film Ba0.25Sr0.75TiO3 voltage tunable capacitors on fused silica substrates for applications in microwave microelectronics

Thin film Au/Pt/Ba_0.25Sr_0.75TiO₃/Pt/Au/Ti capacitor structures were fabricated on fused silica substrates using pulsed laser deposition of ferroelectric films. Low-field dielectric measurements were performed as a function of frequency in the range 1-25 GHz at different external dc fields up to 360 kV/cm. Resonant microwave power absorption observed at frequencies less than 10 GHz under dc field is due to electrostriction and field induced piezoelectric effects. The effects are simulated using an electroacoustic model of the multilayer capacitor structure. A circuit model is applied to investigate the influence of series resistance and inductance of interconnect/lead strips on capacitor performance. Analysis shows that the measured loss tangent of the capacitor is mainly due to series resistance and frequency dispersion of capacitance is caused by series inductance. The de-embedded value of the loss tangent is 0.005 at 10 GHz. The measured loss tangent is less than 0.02 and tunability is up to 40% in the whole frequency range. These parameters indicate high potential of Ba_0.25Sr_0.75TiO₃ capacitors for applications in voltage controlled devices of microwave microelectronics.     

A Fast-Response Logarithmic Electrometer for Pulse-Reactor Experiments

The response time of a logarithmic electrometer was improved for pulse reactor experiments requiring long detector cables. A new phase-compensation technique was used in the circuit and it is based on the idea that a current variable resistance inserted between a detector cable and the input terminal of the logarithmic electrometer recovers the phase lag caused by the input capacitance. This stable and fast-response logarithmic electrometer was successfully applied to transient power measurements of the one-shot pulse-reactor "YAYOI."     

热声发动机驱动阻容负载的实验研究

进行了热声发动机驱动阻容负载的实验研究,分析讨论了阻容负载中声阻和容抗对整机性能的影响.首次通过实验验证了当声阻与容抗相等时,热声发动机向阻容负载传递的声功率最大.以氦气为工质,在充气压力2.1 MPa、加热功率2 000W的条件下,采用110 cm3的气库,在1台驻波型热声发动机上获得了最大43.1 W的声功率输出.     

Empirically-derived capacitor characteristic formulas from distributed modelling

Diffusion equation modelling is used to develop formulas for the normally fixed values of capacitance and resistance of the traditional capacitor equivalent circuit. The formulas define the dependence of the equivalent circuit values on metal film resistivity, capacitance per unit area, areal dimensions of the metallisation and on frequency. A multilayer capacitor topology, having both capacitor plates connected at the same end, is used for the derivation, but it is shown that the results are also representative for the more standard double-end connected topologies with some restrictions above the typical self-resonance frequency of these capacitors. The formulas allow accurate prediction of dissipation factor and input impedance according to the design parameters used in constructing the capacitor, thus providing powerful tools in capacitor design. The algorithms also facilitate the determination of internal voltages, currents and power distribution within the capacitor, thus exposing the effects, for example, of partial edge disconnection. The formulas may potentially provide a better capacitor equivalent circuit with dependent variables for circuit emulation. In the paper, the derivation process is described and the formulas tested against experimental results. A simple addition to the equivalent circuit is also included to model dielectric loss which dominantly determines the dissipation factor at low frequency     

Application of RF varactor using Ba(x)Sr(1-x)TiO3/TiO2/HR-Si substrate for reconfigurable radio

In this paper, the potential feasibility of integrating Ba_xSr_1-xTiO₃ (BST) films into Si wafer by adopting tunable interdigital capacitor (IDC) with TiO₂ thin film buffer layer and a RF tunable active bandpass filter (BPF) using BST based capacitor are proposed. TiO₂ as a buffer layer is grown onto Si substrate by atomic layer deposition (ALD) and the interdigital capacitor on BST(500 nm)/TiO₂(50 nm)/HR-Si is fabricated. BST interdigital tunable capacitor integrated on HR-Si substrate with high tunability and low loss tangent are characterized for their microwave performances. BST/TiO₂/HR-Si IDC shows much enhanced tunability values of 40% and commutation quality factor (CQF) of 56.71. A resonator consists of an active capacitance circuit together with a BST varactor. The active capacitor is made of a field effect transistor (FET) that exhibits negative resistance as well as capacitance. The measured second order active BPF shows bandwidth of 110 MHz, insertion loss of about 1 dB at the 1.81 GHz center frequency and tuning frequency of 230 MHz (1.81-2.04 GHz).