NH3等离子体处理钝化层致Ge MOS界面特性的改善

制备了以TaYON作为钝化层,以HfTiON作为高k栅介质的Ge MOS电容。研究了NH₃和N₂等离子体处理TaYON对界面特性的影响。结果表明,N₂和NH₃等离子体处理可以有效改善器件的界面及电性能,其中,NH₃等离子体处理的效果更好,可获得更高的k值(25.9)、更低的界面态密度(6.72×10¹¹ eV-1·cm-2)和等效氧化物电荷密度(-9.43×10¹¹ cm-2),以及更小的栅极漏电流(5.18×10-5 A/cm²@V_g=1 V+V_fb)。原因在于NH₃等离子体分解产生的N原子或H原子以及NH基团能有效钝化界面附近的悬挂键和缺陷态,防止GeO_x低k界面层的形成,N原子的结合也增加了介质的热稳定性。     

LaON钝化层改善HfTiO高k栅介质Ge MOS电容电特性（英文）

采用溅射法淀积一层LaON薄膜作为钝化层,制备了HfTiO栅介质Ge MOS电容,并对它们的电特性进行了仔细研究。HfTiO/LaON堆栈栅介质Ge MOS电容呈现出许多比HfTiO Ge MOS电容更好的电特性,如更低的界面态密度(4.5×10~(11)eV~(-1)/cm~2)、更小的栅极漏电流(1.08×10~(-5)A/cm~2 at V_(fb)+1 V)和更大的k值(24.8)。获得这些结果的机理在于LaON钝化层能有效阻止O、Ti、Hf和Ge的相互扩散,从而抑制HfGeTiO界面层的生长。HfTiO/LaON是高质量Ge MOS器件有前途的高k栅介质。     

超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

退火气氛对Ge MOS电容电特性的影响

采用反应磁控溅射法在Ge衬底上制备了HfTiO高介电常数k栅介质薄膜,研究了不同气体(N2、NO、N2O)淀积后退火对Ge金属-氧化物-半导体(MOS)电容性能的影响.透射电子显微镜和电特性测量表明,湿N2退火能有效抑制界面层的生长,提高界面质量,改善栅极漏电流特性,从而得到最优的器件性能,即Al/HfTiO/n-Ge MOS电容的栅介质等效氧化物厚0.81 nm,k=34.5,带隙中央界面态密度为2.4×1011cm-2·eV-1,1 V栅偏压下的栅极漏电流为2.71×10-4A·cm-2.     

HfO2/TaON叠层栅介质Ge MOS器件制备及电性能研究

为提高高k/Ge MOS器件的界面质量,减小等效氧化物厚度(EOT),在high-k介质和Ge表面引入薄的TaON界面层.相对于没有界面层的样品,HfO2/TaON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和较好的输出特性.因此利用TaON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的高k/Ge界面质量有着重要的意义.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

基于不同AlN钝化层的极性GaN MOS器件界面特性

界面质量是影响GaN MOS器件性能以及可靠性的主要因素之一,Al203栅介质与极性GaN界面间插入超薄非晶AlN作为钝化层可以有效改善GaN栅界面特性,针对AIN钝化层生长方式研究了GaN界面优化特性.通过GaN MOS电容的C-V和J-V特性,结合透射电子显微镜(TEM)表征分析,对比了不同生长条件的AlN插入层对GaN MOS电容的界面特性的影响.相比常规热生长AlN钝化层制备的样品,以等离子体NH3为N源在300℃下生长AlN钝化层制备的GaN MOS电容的频散和滞回特性均得到显著改善,界面态密度也略有改善.分析认为,经过等离子体NH3的轰击作用有效地抑制了GaN表面上Ga-O键的形成,在GaN表面直接生长AlN,从而改善了界面特性.     

Y_2O_3改善HfO_2高k栅介质Ge MOS电容的电特性及可靠性

以Y_2O_3薄膜作为夹层,采用磁控溅射法制备了HfO_2/Y_2O_3叠层高k栅介质Ge MOS电容,并对其电特性及高场应力特性进行了仔细研究。结果表明,Y_2O_3夹层能显著地改善Ge MOS器件的界面质量、k值、栅极漏电流特性、频率色散特性和器件可靠性。因此,HfO_2/Y_2O_3/Ge MOS电容表现出较低的界面态密度(6.4×1011 eV~(-1)cm~(-2))、较高的k值(21.6)、较小的栅极漏电流密度(Vg=1V+Vfb时,Jg=1.65×10~(-6) A·cm~(-2))、极小的频率色散以及良好的器件可靠性。其机理在于Y_2O_3夹层能充当阻挡层角色,有效地阻挡了Hf、O与Ge的相互扩散,从而抑制了不稳定低k GeO_x夹层的生长。     

中波碲镉汞/钝化层界面电学特性研究

HgCdTe表面/界面特性对器件性能具有重要的影响,表面/界面的状态主要依赖于表面处理和钝化工艺。采用Br2/CH3OH腐蚀液对液相外延(LPE)生长的中波HgCdTe薄膜进行表面处理后,使用Cd Te/Zn S复合钝化技术进行表面钝化,制备了相应的MIS器件并进行器件C-V测试。结果表明,HgCdTe/钝化层界面固定电荷极性为正,面密度为2.1×1011 cm-2,最低快界面态密度为1.43×1011 cm-2·e V-1,在10 V栅压极值下慢界面态密度为4.75×1011 cm-2,较低的快界面态密度体现出了CdTe/ZnS复合钝化技术的优越性。     

表面预处理对Ge MOS电容特性的影响

通过不同气体(NO、N2O、NH3)对Ge衬底进行表面预处理,生长GeOxNy界面层,然后采用反应磁控溅射方法生长HfTiO薄膜,制备HfTiO/GeOxNy叠层高k栅介质Ge MOS电容,研究表面预处理对界面层以及界面层对器件性能的影响.隧穿电子扫描电镜(TEM)、栅电容-电压(C-V)栅极漏电流-电压(J-V)的测量结果表明,湿NO表面预处理能生长高质量的界面层,降低界面态密度,抑制MOS电容的栅极漏电流密度.施加高场应力后,湿NO表面预处理样品的平带漂移及漏电流增加最小,表示器件的可靠性得到有效增强.     

Investigation on interfacial and electrical properties of Ge MOS capacitor with different NH3-plasma treatment procedure

The effects of different NH₃-plasma treatment procedures on interfacial and electrical properties of Ge MOS capacitors with stacked gate dielectric of HfTiON/TaON were investigated. The NH₃-plasma treatment was performed at different steps during fabrication of the stacked gate dielectric, i.e. before or after interlayer (TaON) deposition, or after deposition of high-k dielectric (HfTiON). It was found that the excellent interface quality with an interface-state density of 4.79×10¹¹ eV^-1cm^-2 and low gate leakage current (3.43×10^-5A/cm² at V_g=1 V) could be achieved for the sample with NH₃-plasma treatment directly on the Ge surface before TaON deposition. The involved mechanisms are attributed to the fact that the NH₃-plasma can directly react with the Ge surface to form more Ge-N bonds, i.e. more GeO_xN_y, which effectively blocks the inter-diffusion of elements and suppresses the formation of unstable GeO_x interfacial layer, and also passivates oxygen vacancies and dangling bonds near/at the interface due to more N incorporation and decomposed H atoms from the NH₃-plasma.     

Improved interfacial properties of GaAs MOS capacitor with NH3-plasma-treated ZnON as interfacial passivation layer

The GaAs MOS capacitor was fabricated with HfTiON as high-k gate dielectric and NH₃-plasma-treated ZnON as interfacial passivation layer (IPL), and its interfacial and electrical properties are investigated compared to its counterparts with ZnON IPL but no NH₃-plasma treatment and without ZnON IPL and no plasma treatment. Experimental results show that low interface-state density near midgap (1.17×10¹² cm^-2eV^-1) and small gate leakage current density have been achieved for the GaAs MOS device with the stacked gate dielectric of HfTiON/ZnON plus NH₃-plasma treatment. These improvements could be ascribed to the fact that the ZnON IPL can effectively block in-diffusion of oxygen atoms and out-diffusion of Ga and As atoms, and the NH₃-plasma treatment can provide not only N atoms but also H atoms and NH radicals, which is greatly beneficial to removal of defective Ga/As oxides and As-As band, giving a high-quality ZnON/GaAs interface.     

A thin transition film formed by plasma exposure contributes to the germaniumsurface hydrophilicity

Plasma treatment and 10% NH₄OH solution rinsing were performed on a germanium (Ge) surface. It was found that the Ge surface hydrophilicity after O₂ and Ar plasma exposure was stronger than that of samples subjected to N₂ plasma exposure. This is because the thin GeO_x film formed on Ge by O₂ or Ar plasma is more hydrophilic than GeO_xN_y formed by N₂ plasma treatment. A flat (RMS<0.5 nm) Ge surface with high hydrophilicity (contact angle smaller than 3°) was achieved by O₂ plasma treatment, showing its promising application in Ge low-temperature direct wafer bonding.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

Studies on dielectric relaxation and defect generation for reliability assessments in ultrathin high-k gate dielectrics on Ge

In this work, we present the results of dielectric relaxation and defect generation kinetics towards reliability assessments for Zr-based high-k gate dielectrics on p-Ge (1 0 0). Zirconium tetratert butoxide (ZTB) was used as an organometallic source for the deposition of ultra thin (∼14 nm) ZrO₂ films on p-Ge (1 0 0) substrates. It is observed that the presence of an ultra thin lossy GeO_x interfacial layer between the deposited high-k film and the substrate, results in frequency dependent capacitance-voltage (C-V) characteristics and a high interface state density (∼10¹² cm⁻² eV⁻¹). Use of nitrogen engineering to convert the lossy GeO_x interfacial layer to its oxynitride is found to improve the electrical properties. Magnetic resonance studies have been performed to study the chemical nature of electrically active defects responsible for trapping and reliability concerns in high-k/Ge systems. The effect of transient response and dielectric relaxation in nitridation processes has been investigated under high voltage pulse stressing. The stress-induced trap charge density and its spatial distribution are reported. Charge trapping/detrapping of stacked layers under dynamic current stresses was studied under different fluences (−10 mA cm⁻² to −50 mA cm⁻²). Charge trapping characteristics of MIS structures (Al/ZrO₂/GeO_x/Ge and Al/ZrO₂/GeO_xN_y/Ge) have been investigated by applying pulsed unipolar (peak value - 10 V) stress having 50% duty-cycle square voltage wave (1 Hz-10 kHz) to the gate electrode.     

Atomic oxygen-assisted molecular beam deposition of Gd2O3 films for ultra-scaled Ge-based electronic devices

The atomic oxygen-assisted molecular beam deposition of Gd₂O₃ films on Ge(0 0 1) substrates has been performed at various growth temperatures. The compositional aspects, the interface details and the surface structure have been investigated by in situ X-ray photoelectron spectroscopy, time-of-flight secondary ion mass spectroscopy and in situ atomic force microscopy, and ex situ. The interface layer of GeO₂ has been subsequently fabricated by means of atomic oxygen exposure in order to passivate the high-k/Ge interface. The electrical characterization on the final Gd₂O₃/GeO₂/Ge structure has been reported. The electrical characterization on the Al gate/Gd₂O₃/GeO₂/Ge structure exhibits a MOS behavior, indicating the beneficial effect of GeO₂ passivation.     

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II–VI Tunnel Insulators

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn_0.95Mg_0.05S/ZnS tunnel insulators. The GeO _x -cladded Ge and SiO _x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II–VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II–VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si₃N₄ and SiO₂ layers grown by plasma- enhanced chemical vapor deposition.     

Three-State Quantum Dot Gate FETs Using ZnS-ZnMgS Lattice-Matched Gate Insulator on Silicon

This paper presents the three-state behavior of quantum dot gate field-effect transistors (FETs). GeO _x -cladded Ge quantum dots (QDs) are site-specifically self-assembled over lattice-matched ZnS-ZnMgS high-κ gate insulator layers grown by metalorganic chemical vapor deposition (MOCVD) on silicon substrates. A model of three-state behavior manifested in the transfer characteristics due to the quantum dot gate is also presented. The model is based on the transfer of carriers from the inversion channel to two layers of cladded GeO _x -Ge quantum dots.     

Effect of interfacial oxide on Ge MOSCAP and N-MOSFET characteristics

The effect of electrical quality of interfacial oxide on Ge MOSCAP and MOSFET characteristics is investigated. Different growth conditions are studied to optimize the interfacial layer. CV and D_it measurements are done for accurate comparison of different gate dielectric stacks. Optimized ozone oxidation process is integrated with Co-induced dopant activation to fabricate Ge N-MOSFETs. Forty percent improvement in inversion electron mobility is demonstrated with optimized GeO₂ passivation. The highest electron mobility is reported in bulk Ge N-MOSFETs with GeO₂/Al₂O₃ gate dielectric stack.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.