共查询到18条相似文献,搜索用时 218 毫秒
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针对采用2D-Torus拓扑结构且支持电压频率岛(VFI)的异步片上网络能耗优化问题,提出了具有可靠性的、基于电压频率岛的划分和分配及片上网络任务映射的能耗优化方法.该方法采用递进优化的方式,根据IP核的动态处理能耗,不同电压频率岛之间的转换能耗和可靠性带来的能耗开销定义了IP核在电压频率岛之间移动的阈值函数,并通过对阈值函数进行判断完成电压频率岛的划分和分配,应用基于三元相关性量子粒子群优化算法完成处理单元到资源节点的映射,在映射中考虑保证系统可靠性的通信开销,对异步片上网络系统的可靠性进行优化.实验结果表明,该算法可以在不过多消耗能耗的情况下显著的改善片上网络系统的可靠性,且可有效降低NOC系统的能耗. 相似文献
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片上网络是片上系统SoC通信问题的一种最有效解决方法,如何把知识产权核映射到网格之格件映射问题是NoC设计的关键问题之一。映射问题本质上是一种二次分配的NP难问题,遗传算法能够有效地求解问题的近似最优解。提出一种基于遗传的IP映射算法,实验结果表明,遗传算法能够在几分钟内求得最小能耗的映射。 相似文献
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面向支持电压岛的NoC平台,定义了可靠性约束下的能量感知NoC映射问题,提出一种基于禁忌搜索的优化方法.设计了一种新的能效变化率驱动的启发式算法,嵌套于NoC设计空间的搜索过程中,在IP核映射解的基础上实现各电压岛的电压映射.实验结果表明,本文算法可显著降低NoC能耗,并高效地确保NoC通信的可靠性要求. 相似文献
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片上网络NoC以其高可扩展性成为片上多核的互连解决方案。IP核到NoC结点的映射是片上网络设计的重要阶段。映射对芯片的性能和功耗有重要的影响。本文详细阐述了映射算法的研究现状,给出了映射算法的分类方法,并且分析各种方法的特点。最后,给出一种采用顺序表示的基于遗传算法的NoC映射算法。实验结果表明,该映射算法能够取得较好的准确性和较高的效率。 相似文献
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保证QoS的片上网络低能耗映射与路由方法 总被引:3,自引:0,他引:3
为解决二维mesh片上网络的服务质量和低能耗问题,提出基于最优化搜索的拓扑映射与路由方法Q-LEMR.该方法以降低芯片通信能耗为目标,在保证系统延迟与带宽的服务质量的前提下,自动将给定应用的IP核映射到片上网络结构上,并为通信踪迹定制设计确定的、非死锁的最短路径路由;同时通过加速策略使映射和路由的计算在可接受的时间范围内完成.实验结果表明,Q—LEMR较现有工作平均降低通信能耗28.8%,并满足服务质量要求. 相似文献
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针对复杂片上系统(SoC)芯片的片上网络(NoC)映射方案未考虑测试需求的问题,提出了一种面向测试优化的NoC映射算法,兼顾了可测性的提升和映射开销的最小化。该映射方案首先依据特定的测试结构,使用划分算法进行片上系统所有IP核的测试分组,其优化目标为测试时间最短;之后,再基于分组内IP核之间的通信量,应用遗传算法实现NoC映射,其优化目标是在测试优化的基础上实现映射开销最小。通过多个ITC'02测试基准电路进行的实验结果表明:应用该方案后,测试时间平均减少12.67%;与随机任务映射相比,映射代价平均减少24.5%。 相似文献
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赖国明 《计算机应用与软件》2011,28(12)
片上系统SoC是指在单个芯片上集成了专用处理器、通用处理器、DSP、共享内存块、专用内存块、I/O部件等多个IP核的复杂的系统。规则拓扑的Mesh网格具有布线工整等优点,利用Mesh网格可以很方便地实现复杂的片上系统SoC。知识产权核(Intellectual Property Cores,IP核)到Mesh格件的映射问题是SOC设计的关键问题之一,其本质上是一种二次分配问题的NP难问题,目前没有多项式时间的求优方法。而遗传算法能够有效地求解问题的近似最优解。提出一种基于遗传的映射算法能够在几分钟内求得最小通信能耗的映射。 相似文献
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介绍在基于微控制器IP核的PSTN短消息终端SoC设计当中,如何合理划分硬件和软件的功能;从对微控制器IP核的配置与扩展、片上外设在SFR总线上的映射、存储空间的划分与映射等三个方面,详细讲述SoC的软硬件协同设计。 相似文献
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针对如何将越来越复杂的应用任务有效地映射到片上网络处理单元上,达到以更少的能耗完成任务的目的,提出了一种遗传算法和禁忌搜索算法相融合的新型片上网路低功耗映射算法。该方法充分利用遗传算法强大的全局搜索能力,融合禁忌搜索的局部搜索能力和突出的翻山特性来弥补遗传算法的局部搜索能力弱和早熟的缺陷,取得了更好的片上网络低功耗效果。实验结果表明,在同样的实验平台和功耗模型下,禁忌搜索遗传算法相比于早期的遗传算法能耗降低显著,相比于后来改进的MGA、AGA算法也有能效优势。 相似文献
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We introduce a novel algorithm for dynamic energy management (DEM) under performance constraints in chip multi-processors (CMPs). Using the novel concept of delayed instructions count, performance loss estimations are calculated at the end of each control period for each core. In addition, a Kalman filtering based approach is employed to predict workload in the next control period for which voltage-frequency pairs must be selected. This selection is done with a novel dynamic voltage and frequency scaling (DVFS) algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Using our customized Sniper based CMP system simulation framework, we demonstrate the effectiveness of the proposed algorithm for a variety of benchmarks for 16 core and 64 core network-on-chip based CMP architectures. Simulation results show consistent energy savings across the board. We present our work as an investigation of the tradeoff between the achievable energy reduction via DVFS when predictions are done using the effective Kalman filter for different performance penalty thresholds. 相似文献
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RTOS(Real-Time Operating System,实时操作系统)是SoC(System-on-a-Chip,系统芯片或片上系统)的一个重要组成部分,其功耗一般约占整个系统功耗30~40%的比例,而基于软/硬件划分的RTOS功耗优化方法(简称RTOS-Power划分)能够明显地减少SoC的功耗.因此,文中首先引入了RTOS-Power划分问题的一个新模型,这有助于理解RTOS-Power划分的本质.然后,提出了一种基于离散Hopfield神经网络的RTOS-Power划分方法,重新定义了神经网络的神经元表示、能量函数、运行方程和系数.最后,对该方法进行了仿真实验,并同遗传算法和蚂蚁算法进行了性能比较.实验结果表明:该文提出的方法能够以相对较小的代价(FPGA开销小于4K个可编程逻辑块)取得高达60%的功耗节省,同时,与纯软件实现的RTOS相比,系统性能也得到了相应的提高. 相似文献
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Three-dimensional integrated circuits (3D ICs) are suitable alternatives to traditional two-dimensional (2D) ICs by leveraging its advantage of better performance and packaging; therefore, they have been highly considered by researchers. On the other hand, emerging network-on-chip (NoC) based many-core chips provides great potential for running multiple applications simultaneously. However, using this approach leads to the increase of the interference between applications, resulting in lowering the performance of each application. Hence, mapping tasks belonging to various applications onto the nodes of an architecture is a very important issue. In this study, based on partitioning concept, a novel methodology for mapping of multiple applications at run-time onto an irregular wireless 3D NoC-based multiprocessor system-on-chip (MPSoC) platform in which more than one task can be supported by each processing element (PE) was presented. In the second algorithm (enhanced irregular-partitioning best neighbor), according to the number of applications running simultaneously, the partitioning of network will be dynamically changed to minimize the communication overhead and congestion on the NoC that leads to more efficient task mapping. The simulation results reveal that the second proposed algorithm (enhanced IPBN) in comparison with NPBN (non-partitioning best neighbor) algorithm and our first proposed algorithm (basic IPBN) enhances the performance by decreasing the total execution time, average hop count, average channel load and energy consumption. 相似文献
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Previous standby-sparing techniques assume that all tasks don't access to shared resources. In addition, primary tasks and backup tasks are allocated to the primary processor and spare processor respectively. Spare processor schedules tasks with maximum processor speed. Unlike previous techniques, we have studied the problem of minimizing energy consumption and preserving the original reliability for dynamic-priority real-time task set with shared resources in a standby-sparing system. We propose a novel energy-aware mixed partitioning scheduling algorithm (EAMPSA). Earliest deadline first/dynamic deadline modification (EDF/DDM) scheduling scheme is used to ensure that the shared resources can be accessed in a mutual exclusive manner. Uniformly speed is used to the primary processor and the spare processor. In addition, we use the mixed mapping partitioning of primary and backup tasks method to map tasks. A novel method of mapping task is proposed i.e. the tasks which need to access to shared resources are mapped into the primary processor and the tasks which have no resource requirements are mapped into the spare processor. Furthermore, DVS and DPM techniques are used for both primary and backup tasks to save energy. The experimental results show that the EAMPSA algorithm consumes average 55.43% less energy than that of the SSPT algorithm. 相似文献