Low-frequency noise spectroscopy of polycrystalline siliconthin-film transistors

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Effects of combined x-ray Irradiation and hot-electron injection on NMOS transistors

Changes of NMOS transistor parameters after combined stress of x-ray irradiation and hot-electron injection were studied. We found that, in general, the resultant effects depended strongly on the order of the stress sequence. Of the parameters studied, oxide charge trapping depends more significantly on the stress sequence than the generation of interface traps. Interface trap transformation process and nonuniform defect distribution along the channel have been observed under certain stress conditions. Consequences of the above effects on the transistor dc parameters are discussed.     

Metal evaporation dependent charge injection in organic transistors

To illuminate a long-term remaining issue on how contact metallization (metal and speed) affects charge injection, we investigated top-contact pentacene transistors using two categories of metals deposited at various rates. Differing from previous studies such as those devoted to morphological influences by microscopy, in this work we concentrated on their electrical characteristics in particular combining the low-frequency noise which provided a direct quantity of trap density and its evolution with respect to contact metal and deposition rate. It turns out that the transistors with noble metal (Au) suffer from metal-diffusion related charge trapping in the pentacene bulk close to the Au/pentacene interface, and this diffusion-limited injection is greatly tuned from bulk to interface by speeding Au deposition which leads to a Schottky-like injection due to the severe thermal damage to the upper pentacene layer. Applying a conventional contacting metal (Cu), however, Ohmic contacts with much fewer traps are always observed regardless of metallization speed. This is attributed to an ultra-thin interlayer of Cu_xO that guarantees stable Ohmic injection by introducing gap states and protecting the pentacene film so that those transistors appear to be free from Cu metallization. Our results quantitatively show the limiting factors of charge injection for different metals and at various evaporation rates.     

Tuning electric bistability in pentacene film-based transistor embedding aluminum nanoparticles

Hybrid films of pentacene and aluminum nanoparticles were prepared by depositing pentacene on a SiO₂ surface decorated with aluminum nanoparticles and used as the active channel materials in a thin film transistor. Surface pre-treatment of the aluminum nanoparticles with oxygen plasma and/or organophosphonic acids render the particles surface with different coatings and work functions, which affect the charge trapping/storing ability of the nanoparticles. This in turn results in an electric bistability of the pentacene film-based transistor/memory devices. Correlations of memory window, switching response, and memory retention characteristics with the aluminum nanoparticle surface treatment are provided.     

Effects of film microstructure on the bias stability of pentacene field-effect transistors

In this report, the effects of film microstructure on the bias stability of pentacene field-effect transistors (FETs) were investigated. To control the microstructure of pentacene film, substrate temperature was changed from 25 to 90 °C during pentacene deposition. As the substrate temperature increased, pentacene grain size increased (or grain boundary (GB) decreased) because of the elevated surface diffusion of pentacene molecules. Accordingly, field-effect mobility increased up to 1.52 cm²/V. In contrast, bias stability showed totally different characteristics: samples prepared at high substrate temperatures exhibited the lowest degree of bias stability. This GB independent charge trapping phenomenon was solved by examining molecular scale ordering within the intragrain regions. The pentacene film grown at 90 °C showed the largest percentage of pentacene molecules with bulk crystalline structures. This inhomogeneity in the pentacene microstructure induces crystal mismatch within intragrain region, thereby providing deep trap sites for gate-bias stress driven instability. Our study shows that GB is not the main sites for bias stress related charge trapping, rather the molecular orientation within intragrain region is responsible for the charge trapping events. In this regard, the control of molecular scale ordering is important to obtain OFETs with a high bias stability.     

Organic small-molecule heterointerface for use in transistor-type non-volatile memory

A chargeable layer is an essential element for charge transfer and trapping in a transistor-based non-volatile memory device. Here we demonstrate that a heterointerface layer comprising of two different small molecules can show electrical memory characteristics. The organic heterointerface layer was fabricated with a pentacene and tris(8-hydroxyquinoline) aluminum (Alq3) layers by sequential vapor deposition without breaking the vacuum state. Pentacene was adopted as the active layer on the top, and Alq3 was used as the bottom layer for charge trapping. The bottom-gate top-contact transistor with an organic heterointerface layer showed distinct non-volatile memory behaviors and showed high air stability and reliability. We investigated the energy structure of the pentacene/Alq3 heterointerface layer to reveal the operation mechanism of the non-volatile memory and suggested that the writing/erasing gate bias-dependent energy barrier originating from the difference between the energy levels of the pentacene and Alq3 layers controls the charge transfer at the heterointerface layer. Our approach suggests a simple way to fabricate heterointerface layers for organic non-volatile memory applications with high air stability and reliability.     

Influence of Electric Field on Microstructures of Pentacene Thin‐Films in Field‐Effect Transistors

We report on electric‐field‐induced irreversible structural modifications in pentacene thin films after long‐term operation of organic field‐effect transistor (OFET) devices. Micro‐Raman spectroscopy allows for the analysis of the microstructural modifications of pentacene in the small active channel of OFET during device operation. The results suggest that the herringbone packing of pentacene molecules in a solid film is affected by an external electric field, particularly the source‐to‐drain field that parallels the a–b lattice plane. The analysis of vibrational frequency and Davydov splitting in the Raman spectra reveals a singular behavior suggesting a reduced separation distance between pentacene molecules after long‐term operations and, thus, large intermolecular interactions. These results provide evidence for improved OFET performance after long‐term operation, related to the microstructures of organic semiconductors. It is known that the application of large electric fields alters the semiconductor properties of the material owing to the generation of defects and the trapping of charges. However, we first suggest that large electric fields may alter the molecular geometry and further induce structural phase transitions in the pentacene films. These results provide a basis for understanding the improved electronic properties in test devices after long‐term operations, including enhanced field‐effect mobility, improved on/off current ratio, sharp sub‐threshold swing, and a slower decay rate in the output drain current. In addition, the effects of source‐to‐drain electric field, gate electric field, current and charge carriers, and thermal annealing on the pentacene films during OFET operations are discussed.     

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0 V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.     

Conjugated Polymer Nanoparticles as Nano Floating Gate Electrets for High Performance Nonvolatile Organic Transistor Memory Devices

A molecular nano‐floating gate (NFG) of pentacene‐based transistor memory devices is developed using conjugated polymer nanoparticles (CPN) as the discrete trapping sites embedded in an insulating polymer, poly (methacrylic acid) (PMAA). The nanoparticles of polyfluorene (PF) and poly(fluorene‐alt‐benzo[2,1,3]thiadiazole (PFBT) with average diameters of around 50–70 nm are used as charge‐trapping sites, while hydrophilic PMAA serves as a matrix and a tunneling layer. By inserting PF nanoparticles as the floating gate, the transistor memory device reveals a controllable threshold voltage shift, indicating effectively electron‐trapping by the PF CPN. The electron‐storage capability can be further improved using the PFBT‐based NFG since their lower unoccupied molecular orbital level is beneficial for stabilization of the trapped charges, leading a large memory window (35 V), retention time longer than 10⁴ s with a high ON/OFF ratio of >10⁴. In addition, the memory device performance using conjugated polymer nanoparticle NFG is much higher than that of the corresponding polymer blend thin films of PF/polystyrene. It suggests that the discrete polymer nanoparticles can be effectively covered by the tunneling layer, PMAA, to achieve the superior memory characteristics.     

Structural and Electrostatic Complexity at a Pentacene/Insulator Interface

The properties of organic‐semiconductor/insulator (O/I) interfaces are critically important to the operation of organic thin‐film transistors (OTFTs) currently being developed for printed flexible electronics. Here we report striking observations of structural defects and correlated electrostatic‐potential variations at the interface between the benchmark organic semiconductor pentacene and a common insulator, silicon dioxide. Using an unconventional mode of lateral force microscopy, we generate high‐contrast images of the grain‐boundary (GB) network in the first pentacene monolayer. Concurrent imaging by Kelvin probe force microscopy reveals localized surface‐potential wells at the GBs, indicating that GBs will serve as charge‐carrier (hole) traps. Scanning probe microscopy and chemical etching also demonstrate that slightly thicker pentacene films have domains with high line‐dislocation densities. These domains produce significant changes in surface potential across the film. The correlation of structural and electrostatic complexity at O/I interfaces has important implications for understanding electrical transport in OTFTs and for defining strategies to improve device performance.     

Bipolar charge transport in organic field-effect transistors: Enabling high mobilities and transport of photo-generated charge carriers by a molecular passivation layer

High mobility bipolar charge carrier transport in organic field-effect transistors (OFETs) can be enabled by a molecular passivation layer and selective electrode materials. Using tetratetracontane as passivation layer bipolar transport was realised in the organic semiconductors copper-phthalocyanine, diindenoperylene, pentacene, TIPS-pentacene and sexithiophene and mobilities of up to 0.1 cm²/V s were achieved for both electrons and holes. Furthermore, the trap and injection behaviour was analysed leading to a more general understanding of the transport levels of the used molecular semiconductors and their limitations for electron and hole transport in OFETs. With this knowledge the transistor operation can be further improved by applying two different electrode materials and a light-emitting transistor was demonstrated.Additionally, the effect of illumination on organic field-effect transistors was investigated for unipolar and bipolar devices. We find that the behaviour of photo-excited electrons and holes depends on the interface between the insulator and the semiconductor and the choice of contact materials. Whereas filling of electron traps by photo-generated charges and the related accumulation field are the reason for changes in charge carrier transport upon illumination without passivation layer, both types of charge carriers can be transported also in unipolar OFETs, if a passivation layer is present.     

A two-dimensional numerical simulation of oxide charge buildup inMOS transistors due to radiation

The authors have developed a time-dependent two-dimensional simulator in order to simulate charge trapping in silicon dioxide due to radiation. The Poisson and continuity equations are solved both in the oxide and the semiconductor. In addition, in order to simulate charge trapping, trap rate equations using first-order trapping kinetics are solved in the oxide. This paper contains the numerical methods used in the simulation and results obtained using this simulator. One of the main results of this simulation is the presence of a lateral variation in the radiation-induced oxide charge in an MOS transistor irradiated with a drain bias     

Relaxation effects in NMOS transistors after hot-carrier stressing

Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τrof 600-900 s.     

Direct-current measurements of oxide and interface traps onoxidized silicon

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping     

Molecular-scale charge trap medium for organic non-volatile memory transistors

In this work, we introduce a molecular-scale charge trap medium for an organic non-volatile memory transistor (ONVMTs). We use two different types of small molecules, 2,3,6,7,10,11-hexahydroxytriphenylene (HHTP) and 2,3,6,7,10,11-hexamethoxytriphenylene (HMTP), which have the same triphenylene cores with either hydroxyl or methoxy end groups. The thickness of the small molecule charge trap layer was sophisticatedly controlled using the thermal evaporation method. X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared (FTIR) analysis revealed that there were negligible differences in the chemical structures of both small molecules before and after thermal deposition process. The ONVMTs with a 1-nm-thick HHTP charge trap layer showed a large hysteresis window, approximately 20 V, under a double sweep of the gate bias between 40 V and −40 V. The HMTP-based structure showed a negligible memory window, which implied that the hydroxyl groups affected hysteresis. The number of trapped charges on the HHTP charge trap layer was measured to be 4.21 × 10¹² cm⁻². By varying the thickness of the molecular-scale charge trap medium, it was determined that the most efficient charge trapping thickness of HHTP charge trap layer was approximately 5 nm.     

Bias‐Stress‐Induced Charge Trapping at Polymer Chain Ends of Polymer Gate‐Dielectrics in Organic Transistors

Herein is demonstrated that the polymer chain ends of polymer gate‐ dielectrics (PGDs) in organic field‐effect transistors (OFETs) can trap charges; the bias‐stress stability is reduced without changes in the mobilities of the transistor devices as well as the morphologies of the organic semiconductors. The bias‐stress stabilities of OFETs using PGD with various molecular weights (MWs) are investigated. Under bias stress in ambient air, the drain current decay and the threshold voltage shift are found to increase as the MW of the PGD decreases (MW effect). This MW effect is caused by the variation in the density of polymer chain ends in the PGDs with MW: the free volumes at the polymer chain ends act as charge‐trap sites, resulting in drain current decay during bias stress. The free volumes at polymer chain ends are sufficiently large to allow the residence of water molecules, the presence of which significantly increases the density of charge‐trap sites. In contrast, polymer chain ends without trapped water molecules do not allow charge trapping and so bias‐stress stability is independent of the MW of the PGD. It is also found that the hydrophilicity/hydrophobicity of the chain ends of the PGD can affect bias‐stress stability; carboxyl‐terminated polystyrene exhibits a much higher trap density and lower bias‐stress stability than hydrogen‐terminated polystyrene when these devices are exposed to humid nitrogen.     

Spatial distribution of interface traps in DeMOS transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Study of the electronic trap distribution at the SiO2-Siinterface utilizing the low-frequency noise measurement

A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices with differently prepared gate oxides were used to study the process-induced trap distribution. Several peaks varying from sample to sample are found in a frequency index of noise spectrum versus temperature plot and are correlated with the discrete trap distribution across the bandgap of silicon. This method provides more information on traps as it circumvents the complexity of superimposing different traps which was encountered in the capacitance-voltage (C-V) method. Results, either compatible with others' work or consistent with data based on other measurements, show that the electronic trapping behavior in MOS structures is governed by two intrinsic traps located at 0.12 and 0.3 eV (both measured from the conduction band) for all kinds of oxides. In addition, dry oxidation was found to introduce an additional trap at an energy level of 0.23 eV, and annealing the gate oxide in ammonia at a high temperature (>1000°C) results in an enhancement of the trap density of 0.43 eV below the conduction band edge of silicon, which was also observed in a quasi-static C-V measurement