Synaptic Suppression Triplet‐STDP Learning Rule Realized in Second‐Order Memristors

The synaptic weight modification depends not only on interval of the pre‐/postspike pairs according to spike‐timing dependent plasticity (classical pair‐STDP), but also on the timing of the preceding spike (triplet‐STDP). Triplet‐STDP reflects the unavoidable interaction of spike pairs in natural spike trains through the short‐term suppression effect of preceding spikes. Second‐order memristors with one state variable possessing short‐term dynamics work in a way similar to the biological system. In this work, the suppression triplet‐STDP learning rule is faithfully demonstrated by experiments and simulations using second‐order memristors. Furthermore, a leaky‐integrate‐and‐fire (LIF) neuron is simulated using a circuit constructed with second‐order memristors. Taking the advantage of the LIF neuron, various neuromimetic dynamic processes, including local graded potential leaking out, postsynaptic impulse generation and backpropagation, and synaptic weight modification according to the suppression triplet‐STDP rule, are realized. The realized weight‐dependent pair‐ and triplet‐STDP rules are clearly in line with findings in biology. The physically realized triplet‐STDP rule is powerful in developing direction and speed selectivity for complex pattern recognition and tracking tasks. These scalable artificial synapses and neurons realized in second‐order memristors can intrinsically capture the neuromimetic dynamic processes; they are the promising building blocks for constructing brain‐inspired computation systems.     

Training a Hidden Markov Model with a Bayesian Spiking Neural Network

It is of some interest to understand how statistically based mechanisms for signal processing might be integrated with biologically motivated mechanisms such as neural networks. This paper explores a novel hybrid approach for classifying segments of sequential data, such as individual spoken works. The approach combines a hidden Markov model (HMM) with a spiking neural network (SNN). The HMM, consisting of states and transitions, forms a fixed backbone with nonadaptive transition probabilities. The SNN, however, implements a biologically based Bayesian computation that derives from the spike timing-dependent plasticity (STDP) learning rule. The emission (observation) probabilities of the HMM are represented in the SNN and trained with the STDP rule. A separate SNN, each with the same architecture, is associated with each of the states of the HMM. Because of the STDP training, each SNN implements an expectation maximization algorithm to learn the emission probabilities for one HMM state. The model was studied on synthesized spike-train data and also on spoken word data. Preliminary results suggest its performance compares favorably with other biologically motivated approaches. Because of the model’s uniqueness and initial promise, it warrants further study. It provides some new ideas on how the brain might implement the equivalent of an HMM in a neural circuit.     

低功耗非对称性可调STDP突触电路设计

基于65 nm CMOS工艺设计了一种可用于脉冲神经网络系统的低功耗、高能效、结构紧凑的突触电路.突触电路采用开关电容电路结构,直接接收来自神经元电路的脉冲信号,根据脉冲时间依赖可塑性(STDP)学习规则调节突触权重,并实现了权重学习窗口的非对称性调节,使突触电路可以适应不同情况.仿真结果表明,突触电路耗能约为0.4 ...     

Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit

As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal–oxide–semiconductor (CMOS) circuits using a 3-D “atomistic” coupled device–circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 16-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.      

Solution-processed organic–inorganic hybrid CMOS inverter exhibiting a high gain reaching 890

In this letter, we present a fabrication scheme and device performances of an organic–inorganic hybrid CMOS inverter employing a high-performance p-type organic semiconductor and an amorphous metal oxide layers. A deterioration of the oxide layer during device processing, which is often found in solution-processed semiconductor oxides, can be avoided by a one-shot solution-crystallization technique utilizing a polymer-blend. Both the p- and the n-type channels exhibited excellent transistor performances with high carrier mobilities and with precipitous turn-on behaviors near the gate voltages of 0 V, resulting in a successful demonstration of an ideal CMOS inverter operation with gain of 890. This result will update a potential excellence of organic–inorganic hybrid CMOS circuits in practical devices.     

Low voltage and time constant organic synapse-transistor

We report on an artificial synapse, an organic synapse-transistor (synapstor) working at 1 V and with a typical response time in the range 100–200 ms. This device (also called NOMFET, Nanoparticle Organic Memory Field Effect Transistor) combines a memory and a transistor effect in a single device. We demonstrate that short-term plasticity (STP), a typical synaptic behavior, is observed when stimulating the device with input spikes of 1 V. Both significant facilitating and depressing behaviors of this artificial synapse are observed with a relative amplitude of about 50% and a dynamic response <200 ms. From a series of in-situ experiments, i.e. measuring the current–voltage characteristic curves in-situ and in real time, during the growth of the pentacene over a network of gold nanoparticles, we elucidate these results by analyzing the relationship between the organic film morphology and the transport properties. This synapstor works at a low energy of about 2 nJ/spike. We discuss the implications of these results for the development of neuro-inspired computing architectures and interfacing with biological neurons.     

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.      

Synaptic Learning and Memory Functions Achieved Using Oxygen Ion Migration/Diffusion in an Amorphous InGaZnO Memristor

A single synaptic device with inherent learning and memory functions is demonstrated based on an amorphous InGaZnO (α‐IGZO) memristor; several essential synaptic functions are simultaneously achieved in such a single device, including nonlinear transmission characteristics, spike‐rate‐dependent and spike‐timing‐dependent plasticity, long‐term/short‐term plasticity (LSP and STP) and “learning‐experience” behavior. These characteristics bear striking resemblances to certain learning and memory functions of biological systems. Especially, a “learning‐experience” function is obtained for the first time, which is thought to be related to the metastable local structures in α‐IGZO. These functions are interrelated: frequent stimulation can cause an enhancement of LTP, both spike‐rate‐dependent and spike‐timing‐dependent plasticity is the same on this point; and, the STP‐to‐LTP transition can occur through repeated “stimulation” training. The physical mechanism of device operation, which does not strictly follow the memristor model, is attributed to oxygen ion migration/diffusion. A correlation between short‐term memory and ion diffusion is established by studying the temperature dependence of the relaxation processes of STP and ion diffusion. The realization of important synaptic functions and the establishment of a dynamic model would promote more accurate modeling of the synapse for artificial neural network.     

Double Negative Differential Transconductance Characteristic: From Device to Circuit Application toward Quaternary Inverter

Multi‐valued logic (MVL) computing, which uses more than three logical states, is a promising future technology for handling huge amounts of data in the forthcoming “big data” era. The feasibility of MVL computing depends on the development of new concept devices/circuits beyond the complementary metal oxide semiconductor (CMOS) technology. This is because many CMOS devices are required to implement basic MVL functions, such as multilevel NOT, AND, and OR. In this study, a novel MVL device is reported with a complementarily controllable potential well, featuring the negative differential transconductance (NDT) phenomenon. This NDT device implemented on the WS₂–graphene–WSe₂ van der Waals heterostructure is evolved to a double‐NDT device operating on the basis of two consecutive NDT phenomena via structural engineering and parallel device configuration. This double‐NDT device is intensively analyzed via atomic force microscopy, kelvin probe force microscopy, Raman spectroscopy, and temperature‐dependent electrical measurement to gain a detailed understanding of its operating mechanism. Finally, the operation of a quaternary inverter configured with the double‐peak NDT device and a p‐channel transistor through Cadence circuit simulation is theoretically demonstrated.     

Schottky‐Barrier‐Controllable Graphene Electrode to Boost Rectification in Organic Vertical P–N Junction Photodiodes

Monolayer graphene is used as an electrode to develop novel electronic device architectures that exploit the unique, atomically thin structure of the material with a low density of states at its charge neutrality point. For example, a single semiconductor layer stacked onto graphene can provide a semiconductor–electrode junction with a tunable injection barrier, which is the basis for a primitive transistor architecture known as the Schottky barrier field‐effect transistor. This work demonstrates the next level of complexity in a vertical graphene–semiconductor architecture. Specifically, an organic vertical p‐n junction (p‐type pentacene/n‐type N,N′‐dioctyl‐3,4,9,10‐perylenedicarboximide (PTCDI‐C₈)) on top of a graphene electrode constituting a novel gate‐tunable photodiode device structure is fabricated. The model device confirms that controlling the Schottky barrier height at the pentacene–graphene junction can (i) suppress the dark current density and (ii) enhance the photocurrent of the device, both of which are critical to improve the performance of a photodiode.     

Electrolyte-gated organic synapse transistor interfaced with neurons

We demonstrate an electrolyte-gated hybrid nanoparticle/organic synapstor (synapse-transistor, termed EGOS) that exhibits short-term plasticity as biological synapses. The response of EGOS makes it suitable to be interfaced with neurons: short-term plasticity is observed at spike voltage as low as 50 mV (in a par with the amplitude of action potential in neurons) and with a typical response time in the range of tens milliseconds. Human neuroblastoma stem cells are adhered and differentiated into neurons on top of EGOS. We observe that the presence of the cells does not alter short-term plasticity of the device.     

Inkjet‐Printed Single‐Droplet Organic Transistors Based on Semiconductor Nanowires Embedded in Insulating Polymers

Fabrication of organic field‐effect transistors (OFETs) using a high‐throughput printing process has garnered tremendous interest for realizing low‐cost and large‐area flexible electronic devices. Printing of organic semiconductors for active layer of transistor is one of the most critical steps for achieving this goal. The charge carrier transport behavior in this layer, dictated by the crystalline microstructure and molecular orientations of the organic semiconductor, determines the transistor performance. Here, it is demonstrated that an inkjet‐printed single‐droplet of a semiconducting/insulating polymer blend holds substantial promise as a means for implementing direct‐write fabrication of organic transistors. Control of the solubility of the semiconducting component in a blend solution can yield an inkjet‐printed single‐droplet blend film characterized by a semiconductor nanowire network embedded in an insulating polymer matrix. The inkjet‐printed blend films having this unique structure provide effective pathways for charge carrier transport through semiconductor nanowires, as well as significantly improve the on‐off current ratio and the environmental stability of the printed transistors.     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.     

Bienenstock,Cooper, and Munro Learning Rules Realized in Second‐Order Memristors with Tunable Forgetting Rate

Memristors with synaptic functions are very promising for developing artificial neural networks. Compared with the extensively reported spike‐timing‐dependent plasticity (STDP), Bienenstock, Cooper, and Munro (BCM) learning rules, the most accurate model of the synaptic plasticity to date, are more compatible with the neural computing system; however, the progress in the realization of the BCM rules has been quite limited. The realized BCM rules so far mostly performs just the spike‐rate‐dependent plasticity (SRDP), however, without a tunable sliding frequency threshold, because the memristors used to realize the BCM rules do not have tunable forgetting rates. In this work, the BCM rules with a tunable sliding frequency threshold are biorealistically implemented in SrTiO₃‐based second‐order memristors; the forgetting rate of the memristors is tuned by engineering the electrode/oxide interface through controlling the electrode composition. The approach of this work is precise and efficient, and the biorealistic implementation of the BCM rules in memristors improves the efficiency of the neural network for the artificial intelligent system.     

Artificial Synapses Based on Multiterminal Memtransistors for Neuromorphic Application

Neuromorphic computing, which emulates the biological neural systems could overcome the high‐power consumption issue of conventional von‐Neumann computing. State‐of‐the‐art artificial synapses made of two‐terminal memristors, however, show variability in filament formation and limited capacity due to their inherent single presynaptic input design. Here, a memtransistor‐based arti?cial synapse is realized by integrating a memristor and selector transistor into a multiterminal device using monolayer polycrys‐talline‐MoS₂ grown by a scalable chemical vapor deposition (CVD) process. Notably, the memtransistor offers both drain‐ and gate‐tunable nonvolatile memory functions, which efficiently emulates the long‐term potentiation/depression, spike‐amplitude, and spike‐timing‐dependent plasticity of biological synapses. Moreover, the gate tunability function that is not achievable in two‐terminal memristors, enables significant bipolar resistive states switching up to four orders‐of‐magnitude and high cycling endurance. First‐principles calculations reveal a new resistive switching mechanism driven by the diffusion of double sulfur vacancy perpendicular to the MoS₂ grain boundary, leading to a conducting switching path without the need for a filament forming process. The seamless integration of multiterminal memtransistors may offer another degree‐of‐freedom to tune the synaptic plasticity by a third gate terminal for enabling complex neuromorphic learning.     

Ambipolar Light‐Emitting Transistors of a Tetracene Single Crystal

The first ambipolar light‐emitting transistor of an organic molecular semiconductor single crystal, tetracene, is demonstrated. In the device configuration, electrons and holes injected from separate magnesium and gold electrodes recombined radiatively within the channel. By varying the applied voltages, the position of the recombination/emission zone could be moved to any position along the channel. Because of the changes made to the device structure, including the use of single crystals and polymer dielectric layers and the adoption of an inert‐atmosphere fabrication process, the set of materials that can be used for light‐emitting transistors has been expanded to include monomeric molecular semiconductors.     

Mechanistic Considerations of Bending‐Strain Effects within Organic Semiconductors on Polymer Dielectrics

The development of organic transistors for flexible electronics requires the understanding of device behavior upon the application of strain. Here, a comprehensive study of the effect of polymer‐dielectric and semiconductor chemical structure on the device performance under applied strain is reported. The systematic change of the polymer dielectric results in the modulation of the effects of strain on the mobility of organic field‐effect transistor devices. A general method is demonstrated to lower the effects of strain in devices by covalent substitution of the dielectric surface. Additionally, the introduction of a hexyl chain at the peripheries of the organic semiconductor structure results in an inversion of the effects of strain on device mobility. This novel behavior may be explained by the capacitative coupling of the surface energy variations during applied strain.     

Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

The Ring-Shaped CMOS-Based Phototransistor With High Responsivity for the UV/Blue Spectral Range

The ring-shaped phototransistor with a floating bulk enclosed by a ring-shaped photodiode is proposed to enhance the responsivity for the ultraviolet/blue spectral range. The P-channel metal–oxide–semiconductor field-effect transistor and N-channel metal–oxide–semiconductor field-effect transistor phototransistors were manufactured using a standard 0.35-$mu hbox{m}$ complimentary metal–oxide–semiconductor (CMOS) technology. When the phototransistors were illuminated with 400-nm light, the measurement results for 3-V bias demonstrated a responsivity higher than 1500 A/W, which is also superior to that of other reported photodetectors manufactured using a standard CMOS technology. Even for very small bias voltages such as 0.1 V, the phototransistor can exhibit a responsivity of 17.9 A/W.      

Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime

The p‐type nanowire field‐effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in‐depth technology computer‐aided design (TCAD) with quantum models for sub‐10‐nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence‐band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe‐shell channel p‐type nanowire FET has demonstrated a strong potential for low‐power and high‐speed applications in 10‐nm‐and‐beyond complementary metal‐oxide‐semiconductor (CMOS) technology.