A Hardware Acceleration Platform for Digital Holographic Imaging

This paper presents a hardware acceleration platform for image reconstruction in digital holographic imaging. The hardware accelerator executes a computationally demanding reconstruction algorithm which transforms an interference pattern captured on a digital image sensor into visible images. Focus in this work is to maximize computational efficiency, and to minimize the external memory transfer overhead, as well as required internal buffering. The paper presents an efficient processing datapath with a fast transpose unit and an interleaved memory storage scheme. The proposed architecture results in a speedup with a factor 3 compared with the traditional column/row approach for calculating the two-dimensional FFT. Memory sharing between the computational units reduces the on-chip memory requirements with over 50%. The custom hardware accelerator, extended with a microprocessor and a memory controller, has been implemented on a custom designed FPGA platform and integrated in a holographic microscope to reconstruct images. The proposed architecture targeting a 0.13 µm CMOS standard cell library achieves real-time image reconstruction with 20 frames per second.     

基于FPGA的小波去噪的硬件实现

为了解决传统频域去噪法在光信号处理中单分辨率的局限性,提出了具有多分辨性的小波去噪法,并通过对比验证其有效性。由于小波去噪实现对硬件的要求较高,采用现场可编程门阵列做硬件平台来实现基于分布式算法的小波运算,将复杂的乘法运算转化为简单的并行查表累加过程,提高了运算效率,完成了小波算法的硬件移植。最后设计了基于现场可编程门阵列的采集系统,并在其上进行了小波去噪的硬件验证。结果表明,小波去噪算法在现场可编程门阵列平台上得到了很好的实现,且去噪效果良好。     

基于远程云端FPGA平台的EDA在线实验研究

为打破EDA硬件实验的时空限制,拓展EDA实验项目的广度和深度,提出了基于远程云端FPGA实验平台的EDA在线实验模式。介绍了实验平台软、硬件系统架构及基于该平台的EDA实验流程,列举了新平台下的实验项目,并给出了一个实验示例。实际运行结果表明,该平台对提高学生的学习兴趣、培养他们的自主学习和动手实践能力具有较明显效果。该平台还可以推广到其它基于FPGA的硬件类相关课程的实验教学。     

Built-in Self Test Based on Multiple On-Chip Signature Checking

We propose an improved BIST architecture which supports on-chip comparison of signatures at no significant increase in area. The proposed test architecture reduces detection latency and eliminates the lengthy scan-out phase from each test session by allowing testing and on-chip signature comparison of multiple intermediate signatures to occur concurrently. The work is based on a novel procedure to implement the multiple on-chip signature checking. We show that such a test method gives significant improvements in test application time and aliasing probability. This paper also presented two techniques to minimize the test area overhead with a very small test time overhead compare to the conventional schemes. These techniques resulted in up to 80% savings in test area overhead for some High-level synthesis benchmark circuits. This paper also presents an aliasing analysis of the proposed scheme.     

Dynamic Partial Reconfigurable FFT for OFDM Based Communication Systems

This paper presents a novel scalable and runtime dynamically reconfigurable FFT architecture for different wireless standards. With only 8 butterfly units, a reconfigurable FFT architecture for three different FFT points is realized using mixed radix-2²/2³/2⁴ FFT algorithm in a modified Single-path Delay Feedback (SDF) pipelined architecture. Via a proper data flow reconfiguration it can support 64, 128 and 256. It can even be extended up to 8192-point transforms and uses only 13 butterfly units to realize 8192 points. This paper describes the implementation method of 256 and 128 point FFT, which is reconfigured partially from 64 point FFT. The whole system is implemented on a Xilinx XC2VP30 FPGA device. The implementation design addresses area efficiency and flexibility allowing the insertion of the partial modules dynamically to realize various FFT sizes. To verify the efficacy of this dynamic partial reconfigurable FFT design method, a conventional multiplexer based reconfigurable architecture was designed and tested on the same platform. Tested FPGA results for the Dynamic Partial Reconfigurable (DPR) method show the configuration time improvement and good area efficiency as compared to the reconfigurable architecture using conventional multiplexer techniques.     

基于FPGA的红外目标自动检测系统

红外成像在军民监控领域广泛应用,红外自动目标检测能减少人工参与,有效提高效率.本文实现了基于FPGA的红外目标检测系统,首先对系统的硬件资源需求进行评估,并设计了以FPGA为核心处理器的系统硬件平台.其次,开发了基于FPGA的红外目标自动检测处理流程,经过两点校正与盲元补偿等预处理后的红外图像信号,通过混合高斯背景建模的方法建立背景模型,自动检测前景目标,再将目标区域周围高亮标识出来.实测结果表明,该系统可有效检测出高亮背景下的红外目标.     

基于FPGA的红外图像细节增强算法设计与实现

双边滤波算法是一种有效的红外图像细节增强算法,具有保边去噪的效果。但由于算法运算量大,在红外视频图像处理中较难实现。本文提出了一种双边滤波+平台直方图均衡的红外图像增强算法的FPGA实现方法,选用Xilinx Virtex-5系列芯片,采用流水线和并行处理技术,能够在40 ms内完成一帧640×480的14位图像的处理,有效提升红外图像的清晰度和对比度,并满足视频图像处理算法的实时性要求。     

红外预警实时图像处理系统设计与实现

以Xilinx公司的Virtex 5系列FPGA与TI公司TMS320C6455型高速DSP为核心处理器设计多核架构的应用于周扫式红外预警系统的实时图像处理平台。设计过程中,在FPGA内部引入多路扫描机制取代传统周扫式红外预警实时图像处理系统所采用的等待机制以改善系统的实时性;处理器间按SRIO协议实现高速通信,最终处理结果通过PCI-e传输模式发送至主控计算机。实验表明,所设计平台能够满足周扫式红外预警系统实时性要求且在反应时间、虚警率和漏警率方面优于传统实时图像处理平台。     

基于SoC的FBG传感网络解调系统设计

为了有效解调FBG传感阵列,提出了一种基于片上系统SoC的FBG图像解调系统方案,可在FPGA硬件平台上实现图像采集、通信等功能,将FBG阵列的波长解调转化为FBG光斑图像解调.实验表明,该系统精度高、复用能力强.     

多模复合末制导图像处理系统设计与实现

在末制导图像处理系统中,单模系统会带来匹配精度不够、容易受干扰等问题,采用多模系统进行融合决策,是提高跟踪定位精度和抗干扰能力的更优选择。本文基于多DSP和FPGA,提出采用接口管理和图像匹配分开的分布式管理架构,设计实现了可兼容光学、射频模式的多模复合末制导图像处理系统,系统具有高实时性、可重构性和通用性强的特点。同时,在设计的系统平台上,采用适合各模式的FPGA预处理算法完成图像实时预处理,采用SIFT特征匹配算法完成实时并行匹配运算。实验表明,本文设计的末制导图像处理系统及SIFT特征匹配算法,在光学和射频模式下都达到了实时处理的要求;复合末制导处理系统的匹配精度,要优于单模末制导图像处理系统的匹配精度。     

JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题,该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制,从面积和功耗两方面减小了硬件实现的开销。在实现中,采用基于行的提升变换结构和比特平面并行的编码方式,提高了效率,确保整个过程的实时处理。实验结果表明：在实时编码要求下,对分辨率为512512的图像分片进行四级9/7或者5/3小波分解,码块大小为3232,采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证,且系统时钟可以工作在100MHz。     

一种双核SoC调试系统的设计与验证

调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。     

一种高效流水低存储的JPEG2000编码芯片设计

该文提出了一种高效流水低存储的JPEG2000编码芯片的设计方案。该方案通过采用双缓存的小波系数存储结构,预速率控制方法,Tier2中的RD斜率值的字节表示,以减少片上存储器;对离散小波变换,算术编码和位平面编码使用高度并行流水等设计结构以提高编码单元电路速度;字节地址空间的RD斜率值搜索提高了Tier2的打包速度;对系统实现中的时钟分配,色度转换,帧存储器控制进行了优化设计。基于该设计方案的整个编码芯片已通过FPGA验证,主要性能参数：小波类型为5/3,支持最大Tile为256256,最大图像40964096,码块为3232,系统采样率在Tier1工作时钟为100MHz时可达45Msamples/s,压缩图像与JASPER在压缩20倍时相比均小于0.5dB,在SMIC.25库综合下,等效门为10.9万,片上RAM为862kb。     

基于SOPC可重构的图像采集与处理系统设计

针对目前PC算法无法实现图像实时处理以及固定硬件平台很难实现算法修改或者升级的问题,设计一种基于SOPC可重构的图像采集与处理系统,实现了图像数据的片上实时处理以及在不改变硬件电路结构而完成算法修改或者升级的功能。此系统围绕两块Xilinx FPGA芯片进行设计,通过FPGA以及其Microblaze 32 bit软核处理器和相关接口模块实现硬件电路设计,结合FPGA开发环境ISE工具和EDK工具协作完成软件设计。由于采用SOPC技术和可重构技术,此设计具有设计灵活、处理速度快和算法可灵活升级等特点。     

一种无匹配时间损耗的DFA压缩算法的研究与实现

高性能深度包检测系统使用确定型有穷自动机DFA（Deterministic Finite Automata）来执行数据包的检测过程.然而,DFA所带来的存储消耗问题使其难以适用于片内资源稀缺的FPGA.目前已存在多种算法着眼于解决DFA的空间爆炸问题,但是其在带来较好压缩率的同时,也在一定程度上影响到了系统的检测速度.本文提出了一种无匹配时间损耗的DFA压缩算法,并在此基础上,基于FPGA硬件平台,设计实现了单个DFA匹配引擎.实验测试结果表明,本文所设计的算法,在未影响整个系统匹配性能的前提下,可以实现10%~30%左右的压缩率.     

A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration

A multilayer run-time reconfiguration architecture (MRRA) is developed for autonomous run-time partial reconfiguration of field-programmable gate-array (FPGA) devices. MRRA operations are partitioned into logic, translation, and reconfiguration layers along with a standardized set of application programming interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. In particular, FPGA configurations can be manipulated at runtime using on-chip resources. A corresponding logic control flow is developed for a prototype MRRA system on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Evaluations of these prototypes on a number of benchmark and hashing algorithm case studies indicate the enhanced resource utilization and run time performance of the developed approaches.     

High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.     

Run-Time Integration of Reconfigurable Video Processing Systems

Embedded systems in field-programmable gate arrays (FPGAs) can be customized and adaptive if assembled from modular components at run time. This paper examines realizing run-time system assembly by extension of platform-based design. Two major challenges are addressed in this paper. First, the design of a reconfigurable platform architecture suitable for run-time system assembly is described. Different systems are constructed by integrating the platform architecture with different modular components, which employ the communication infrastructure supplied by the platform in order to interact. Second, where on-chip communications channels use shared media, we propose techniques for modeling the intermodule communication behavior based on statistical time-division multiplexing. The proposed techniques enable system designers to guarantee that logical communication requirements between the adjunct modules can be satisfied by the infrastructure. An in-depth analysis is presented and then verified with cycle-accurate simulations for an example reconfigurable platform for real-time video applications.     

基于ADSP-BF609的指针式仪表识别系统设计

指针式仪表数字化是通过图像采集与处理技术来读取与识别,能够提高判读准确性和效率,避免主观原因产生的误差。文中提出了一种基于DSP的指针式仪表识别系统的设计方案,采用中值滤波进行图像去噪,Canny算子进行边缘检测,Hough变换进行圆心定位和直线检测等指针仪表识别算法。借助ADI公司提供的集成开发环境CCES对系统的功能和性能进行测试。结果表明,该平台运行稳定,基于DSP的指针图像识别具有较强的准确性和实时性。     

ANFIS based quadrotor drone altitude control implementation on Raspberry Pi platform

The unmanned aerial vehicles can have complicated dynamics and kinematics that governs the flight of such multirotor devices. PID type controllers are one of the most popular approaches with Raspberry Pi 3 platform for stability of the flight. However, in dynamic environment they are limited in performance and response times. The autonomous tuning of the controller parameters according to the state of the environment with assistance of the adaptive neuro-fuzzy inference system is a well known approach. This paper provides implementation details and feasibility of such a controller with Raspberry Pi 3 platform for use in geological wireless sensing environments. The proposed neuro-fuzzy controller is developed for a Raspberry Pi 3 platform and tested on a physical quadrotor drone and compared to the conventional PID controller during flight.