一款任意层互连HDI板制作及流程管控

任意层互连板是印制板中制作难度大、工艺技术水平高的一种。文章选取一款用于移动通信智能终端的任意互连板,对其流程制作和品质管控做了初步阐释,希望能给业界同行提供一定的参考。     

第十五讲:BUM板的可靠性

具有好的热和电的可靠性BUM板是PCB工业走向高密度或高密度互连(HDI)方向的一个最本质的方面,也是PCB工业走上新一代产品的最根本的问题。而BUM板的可靠性主要集中于高密度微孔(microvia)互连的可靠性上,而高密度微孔互连可靠性是与积层(Redistribution Layer,再配置层)材料特性、微孔加工技术和微孔互连(层间)形成过程密切相关。本文将概要地介绍BUM板可靠性测试方法和结果。由于BUM板诞生以来时间不长,还处于开发和发展时期,还不很成熟,标准、规范和可靠性测试方法等还要有一定时间。因此,目前BUM板的可靠性试验仍然沿用或采用常规     

文献与摘要（155）

复杂PCB制造中使用常规的逐层层压方法与导电胶互连方法的成本比较 印制电路板层间互连孔的导通有通过孔中电镀铜和孔中填充导电膏方法,或两者组合实现,这些不同的方法各有优势。在生产技术保证的条件下,需要寻找降低制造成本目标。本文从作业成本和参数成本两个主要方面,对HDI板微孔电镀铜互连和填充导电膏互连进行加工成本分析比较,结合手机的10层HDI板和28层服务器主板两个案例的分析,说明导电膏互连比电镀铜互连有成本优势。     

高速高密度数字集成电路中的互连效应分析软件—Emulator

本文介绍了一种用于分析高速高密度数字集成电路中的互连结构对所传输信号产生的影响的软件——Emulator.互连结构的电磁参数提取采用直线法,引入了等效传输线的概念,因此可以方便地分析具有任意层介质和任意根导体的多层互连结构.在提取电磁参数的基础上,采用双重波形松驰法计算了端接非线性负载时互连的瞬态响应.对一个集成电路中多层互连结构的分析结果表明,Emulator具有准确、使用方便和计算效率高等优点.有较强的实用价值.     

适用于0.8μmCMOS VLSI的双层金属布线技术研究

多层金属有线互连技术是VLSI工艺中最重要和关键的技术之一．本文系统地研究了用效0．8μmCMOSVLSI的双层金属布线工艺技术，特别是对双层金属布线层间介质的平坦化、接触孔和通孔的低阻欧姆接触及可靠的金属互连等关键工艺进行了分析讨论．这套技术已成功地应用放“0．8μm双层金属布线CMOS计算机主板时钟产生器专用集成电路”的研制，并获得较好芯片成品率．     

低温共烧陶瓷多层基板精细互连技术

微电子技术和封装工艺的发展使超大规模集成电路(VLSI)的密度越来越高,而高密度低温共烧陶瓷(LTCC)基板的制作依赖于基板内部导体的精细互连技术.为了满足LTCC多层基板高密度互连的工艺要求,必须使基板微通孔的直径及导线线宽缩小到100 μm以内.基于此,首先介绍了LTCC生瓷带层的微通孔形成与填充工艺,以及所形成的微通孔的特点;利用厚膜丝网印刷技术形成精细导线,分析了影响印刷质量的工艺参数;最后简要介绍了薄膜光刻等新技术.通过应用上述几种先进的精细互连工艺技术,极大地提高了LTCC多层基板的互连密度.     

印制电路板局部高密度互连的新方法

通过将PCB和高密度互连膜局部粘附到一起（LST－HDI－PCB），使得传统的印制电路板（PCB），如象陶瓷基板和环氧玻璃板，实现了局部高密度互连，这是解决印制电路板高密度互连（HDI－PCB）需求的一种新方法。这种概念可为传统的PCB任意区域提供HDI。在该技术中，使用了Cu/Pl(铜／聚酰亚胺）膜，可把Cu/PI膜层压到传统PCB上任意需要HDI的区域。按照这种新方法，使用批量生产线可同步制造传统的PCB和HDI－Cu/PI膜，其带来的成本优点胜过逐次组装的板子。目前我们开发的Cu/PI膜技术可在PI膜上沉积不同厚度的Cu层，而且没有针孔。这种技术特别适用于超细线和超细间距应用领域。此外，可对Cu/PI膜进行化学蚀刻及用激光打孔形成直径达50微米（micro)(2mil)的微孔，微孔和超细线及超细间距可实现超高密度的互连。在这种技术中，最细线和最线间距达10micro(0.4mil),使电路间距达到了20micro(0.8mil)。本讨论了完全用高I／O BGA、CSP及小型SMT器件组装的测试载体在开发研制过程中所遇到的问题和竞争的焦点以及该技术的发展现状。此外，还详细地论述了制造工艺和生产能力。     

微波组件的关键组装工艺技术

介绍了微波组件组装过程中的关键工艺技术,包括大面积接地互连技术、芯片贴装技术、引线键合互连技术以及密封技术,对每种工艺技术又分别介绍了几种常用实现方法,并阐述了每种工艺方法的机理以及各自的优缺点,以及影响组装质量的主要因素和优化方法。     

小于100ns的256KDRAM

本章将描述用单层多晶硅或双层多晶硅,低阻多层互连及2微米工艺技术制造的256k×1动态RAM,也将讨论容错技术,半字节模式和超前于RAS的CAS刷新选择。     

微波器件高频多层板制造工艺研究

随着现代通讯技术的飞速发展,高频基板材料、以及高频基板材料印制板的制作工艺技术,成为现阶段业界同仁关注的焦点。本文就,高频多层印制板制造用原材料-泰康利公司高频介质材料TSM-DS3,进行了性能及特点介绍。在此基础上,对选用此类高频介质基板材料及半固化片Fast Rise-28,制造高频多层印制板的工艺技术,进行了较为详细的介绍。最后,还针对此次高频多层印制板制造过程中的关键工艺技术进行了较为详细的阐述,其中包括有TSM-DS3-50OHM高频电阻材料的平面电阻阻值控制技术、高频材料的多层化实现技术变形控制技术、多层板孔金属化互连实现的背钻深度控制技术、以及多层印制板局部外形侧壁金属化技术等。     

Fabrication and characterization of low-cost ultrathin flexible polyimide interposer

A passive interposer, which is a way to bridge the feature gap between the integrated circuit (IC) and the package substrate, is a key building block for high performance 3-D systems. In this paper, polyimide (PI) is proposed as an alternative to glass and silicon based interposers for cost-effective 2.5-D/3-D IC integration. The development of interconnect technology using an ultrathin flexible polyimide interposer (UFPI) for 2.5-D/3-D packaging applications is described in detail. A semi-additive process consisting of copper seed layer deposition, photolithography, and electrolytic copper pattern plating is used for fabricating a double-sided flexible fan out interposer. A UFPI with electrodeposited micro-scale copper (Cu) fine patterns and laser drilling microvia is investigated using a scanning electron microscope (SEM), energy-dispersive spectrometry (EDS), X-ray spectrometry, and an optical 3-D profilometer. The UFPI with fine pitch on 12.5 μm thin PI substrates has been demonstrated. The result is a proof-of-concept to exploit the opportunities of cost-effective 2.5D flexible interposer production.     

AOI技术在激光微孔产品检查中的应用

在过去几年里,小型PCB诸如硅芯片级以及便携式移动电话的生产者和设计者们已经发现:如果要保持自己的竞争力并具备生产高密度封装板能力,就必须采用微孔技术。微孔技术的出现要求针对微孔缺陷的有效检测手段对工艺进行过程控制。本文对激光微孔的自动光学检测进行了详细介绍。     

0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

Improved a priori interconnect predictions and technology extrapolation in the GTX system

A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density, and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC technology extrapolation system (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects.     

微导通孔的电镀填孔技术

本文主介绍了电镀填孔技术,并探讨了DC和PPR电镀填孔技术的优缺点和影响填孔效果的相关因素。     

填孔电镀光剂研究进展

文章简述了填孔电镀的机理模型,分析了光亮剂、整平剂和载运剂的作用及失效机制,以期加深广大PCB业者对盲孔填孔电镀技术的了解。     

HDI PCB制造中采用TEA CO2激光的铜直接钻孔

研究了采用二氧化碳（CO2）激光在高密度互连（HDI）印制板（PCS）的铜导体层上有效的微导通孔形成的铜直接钻孔的方法。在铜导体箔的表面上镀覆金属锡层,以便增进铜导体箔上的CO2激光能量吸收。镀层表面采用各种脉冲能量的CO2激光进行钻孔。采用一种激光脉冲可以在9μm厚度的抛光铜导体层上有效地形成优质的微导通孔。     

Effects of build-up printed circuit board thickness on the solderjoint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer     

Metallization of microvias by sputter-deposition

In high-density interconnection technologies the size of via holes significantly effects the space available for component assembly. Commonly used CO₂ lasers do not produce microvias small enough for future demands. In this paper we investigate metallization of UV-laser drilled microvias by magnetron sputtering.The core material of the test boards was a copper-clad FR-4 laminate. The boards were coated with two types of nonphotoimageable liquid dielectrics. A thin chrome layer (0.1 μm) with a subsequent copper layer (3 μm) or copper layer without any intermediate chrome layer was sputtered onto the surfaces and within the microvias. Copper was electrolytically grown onto the sputtered metal layers. In fine lines the adhesion of the metallic layer to the core material is essential. Our earlier studies have shown that chrome has good adhesion to epoxy and it is used as a seeding layer between epoxy and sputtered copper.The purpose of our research is to assess the usefulness of sputtering techniques for metallizing small vias and to find a combination of dielectric material, technologies for microvia formation and plating for achieving reliable microvia connections. Microvias were analyzed after every process stage by means of a microscope and a scanning electronic microscope.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.