A low-power ADPLL using feedback DCO quarterly disabled in time domain

We propose a low-power ADPLL (all-digital phase-locked loop) using a controller which employs a binary frequency searching method in this paper. Glitch hazards and timing violations which occurred very often in the prior ADPLL designs are avoided by the control method and the modified DCO (digital-controlled oscillator) with multiplexers. Besides, the feedback DCO is disabled half a cycle in every two cycles so as to reduce 25% of dynamic power theoretically. The proposed design is implemented by only using the standard cells of a typical CMOS process. The feature of power saving is verified on silicon to be merely 1.53 mW at a 133 MHz output.     

Switch fault detection and diagnosis in space vector modulated cascaded H-bridge multilevel inverter

This article investigates the development and online implementation of the power switch open-circuit fault detection and diagnosis in symmetric cascaded H-bridge multilevel inverter. A mathematical modelling technique is presented to understand the effect of the fault on the bridge voltages and output voltage. The modelled values of the output voltage, simulation results and experimental results indicate that the fault diagnostic methods based on the output voltage as the diagnostic feature have certain ambiguity in identifying the fault switch, since the output voltage waveform and its features remain the same for a group of switches under the fault condition. In order to overcome this, fault detection and diagnosis method based on the mean values of the bridge voltages is proposed in this article, which identifies the faulty switch pair and H-bridge in which the fault has occurred. Further, this method has been experimentally validated on a five-level space vector modulated symmetric cascaded H-bridge multilevel inverter.     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

一种基于偏移源的频率合成技术分析

针对一种基于偏移源的频率合成技术,建立了锁相环(PLL)线性模型,对相位噪声和杂散信号性能进行分析。从分析结果看,在锁相环反馈支路中使用一个偏移源将压控振荡器(VCO)输出信号下混频至一个较低的中频,从而将锁相环的环路分频比大大降低,使改善后的锁相环噪底达到-135 dBc/Hz。介绍了偏移源和主环的关键合成技术,结合工程应用设计的基于偏移源的C频段频率合成器,相位噪声偏离载波10 kHz处≤-99 dBc/Hz,偏离载波100 kHz处≤-116 dBc/Hz,杂散小于-70 dBc。     

一种X波段频率合成器的设计方案

在非相参雷达测试系统中,频率合成技术是其中的关键技术.针对雷达测试系统的要求,介绍了一种用DDS激励PLL的X波段频率合成器的设计方案。文中给出了主要的硬件选择及具体电路设计,通过对该频率合成器的相位噪声和捕获时间的分析,及对样机性能的测试,结果表明该X波段频率合成器带宽为800 MHz、输出相位噪声优于-80 dBc/Hz@10 kHz、频率分辨率达0.1 MHz,可满足雷达测试系统系统的要求。测试表明,该频率合成器能产生低相噪、高分辨率、高稳定度的X波段信号,具有较好的工程应用价值。     

一个新结构低功耗2.5 GHz CMOS LC压控振荡器的设计

压控振荡器是锁相环电路的关键的组成部分之一,采用新的电流复用结构,可以明显降低该电路的功耗,而且由于没有尾电流,新结构还能有效改善电路的相位噪声.在TSMC 0.18 CMOS 1P6M工艺下的仿真结果表明:在1.25 V供电电压下振荡器的调节范围是2.26 GHz到2.76 GHz,在频偏1 MHz处的相位噪声为--130 dBc/Hz,平均功耗不超过1.2 mW.     

基于低功耗约束的CMOS LNA的优化设计

针对低功耗电路发展的趋势,在传统的共源共栅结构基础上,同时引入实现噪声优化的PCSNIM技术和提高增益的级间匹配技术,通过合理调节晶体管的尺寸实现了低功耗的指标.电路采用TSMC 0.18 μm CMOS工艺进行设计,模拟结果表明,在2.45 GHz工作频率下,输入输出匹配良好,增益为14.274 dB,噪声系数为0.669 dB,1 dB压缩点为-16.1 dBm,IIP3为-4.858 dBm,直流功耗仅2.628 mW.     

DSP-based control of a high frequency three cell flying capacitor inverter

The design, instrumentation and early operation results of a digitally controlled voltage source inverter (VSI) are described. This inverter has been structured from a three cell flying capacitor inverter (TCFCI). Two different inverter control modes – open-loop and closed-loop – are applied by a digital system based on a Texas Instrument TMS320C6713 digital signal processor (DSP) board. The VSI is able to generate AC voltage signals up to 120 V amplitudes at a maximal 6 A current, from ～9 kHz to ～60 kHz in ～900 Hz steps in both controls by varying the signal period through the square-wave command strategy. The multi-cell structure of the inverter provides an output frequency nearly three times that of the TCFCI semiconductor commutation. The power output of the TCFCI can drive a high frequency step-up transformer which, in turn, is associated with a cylindrical reactor where dielectric barrier discharges (DBD) are conducted.     

频率合成相噪相消技术研究

提出了一种新型的基于相位噪声抵消技术的频率合成器设计方法,该方法采用一个相参的锁相环信号在两次频率变换过程中得到输出信号相位噪声的抵消。对相位噪声抵消技术进行了理论分析,并搭建了一个100~2900 MHz 宽带小步进频率源。实验结果表明,在偏离主频10 kHz、100 kHz 处,相位噪声抵消了约20 dB,实验证明该技术对中近区相位噪声抵消效果明显,为超低相噪频率合成器设计提供了一种新的思路。     

一种2.4-GHz全集成双环路频率综合器的设计

根据不同锁相环频率综合器架构各自的优缺点,选择了双环路锁相环结构以获得低相位噪声和快速锁定时间。采用0.18μm CMOS工艺设计了一款2.4 GHz全集成双环路锁相环频率综合器,由主锁相环和参考锁相环环路构成。采用MATLAB和SpectreRF对锁相环系统的相位噪声、锁定时间进行了仿真,得到主锁相环输出频率为在2.4 GHz时,相位噪声为-120 dBc/Hz@1 MHz,功耗为10 mW,电源电压为1.8 V。频率范围为2.4 GHz至2.5 GHz,RMS相位误差为1°,锁定时间为5μs。     

Elimination of truncation and round off error and enhancement of stability using a new split loop DPLL

In contrast with the conventional split loop digital phase lock loop, a new loop is presented in this paper that differs from the earlier version principally by design aspects. It incorporates an additional phase modulation input along with its frequency modulation input in the digital controlled oscillator. It is capable of eliminating the deleterious effects of rounding and truncation error with faster signal accusation. Higher loop stability is also achievable using the new split loop digital phase lock loop. Furthermore, radio frequency filtering is done using an In phase and Quadrature phase (IQ) voltage controlled oscillator to avoid interaction between the loop filter and the radio frequency filter. Copyright © 2011 John Wiley & Sons, Ltd.     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

一种用于数字助听器SoC的高性能低功耗、可配置自动增益控制环路

A low-power,configurable auto-gain control loop for a digital hearing aid system on a chip(SoC) is presented.By adopting a mixed-signal feedback control structure and peak detection and judgment,it can work in automatic gain or variable gain control modes through a digital signal processing unit.A noise-reduction and dynamic range(DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply.The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process.The measurement results show that in a 1 V power supply,1.6 kHz input frequency and 200 mVp-p,the SFDR is 74.3 dB,the THD is 66.1 dB,and the total power is 89 μW,meeting the application requirements of hearing aid SoCs.     

环形压控振荡器的噪声分析

在振荡器的设计中,为了得到更高性能,分析其相位噪声是十分重要的.利用Razavi对具有普遍意义的品质因数的定义将Leeson针对LC振荡器提出的相位噪声模型应用到环形振荡器上对其进行噪声分析.文中以一个2 GHz环形振荡器为例,采用TSMC 0.25 μm CMOS工艺参数,用Cadence的spectre仿真器进行仿真.电源电压为2.5 V,偏离中心频率1 MHz处的相位噪声为-86.6 dBc/Hz.仿真的结果与噪声模型所的结果基本吻合.     

一种C波段小步进捷变频频率综合器的设计

本文介绍了一种小步进、低相噪、低杂散、捷变频锁相频率综合器的设计与实现,本设计选用超低相噪锁相环芯片,采用小数分频实现小步进,通过双锁相环“乒乓”工作实现捷变频,经过对环路参数的精心设计,较好的实现了相位噪声、杂散等技术指标。     

有线数字电视用CMOS锁相环及其相位噪声分析

论文设计了一个满足有线数字电视接收的CMOS锁相环集成电路。针对DVB-C接收标准,细化了电荷泵锁相环的相位域模型,根据该模型推导了各模块噪声的传输函数;对锁相环各模块的噪声特性进行了分析,根据相位误差优化目标,提出了优化重点。测试结果表明,在整个电视接收带宽内根据分析结果来优化的锁相环相位误差小于3.9°。内含该锁相环的电视调谐器实现了对DVB-C64QAM数字电视信号清晰接收。     

基于新型延迟电路的CMOS片上温度传感器

为在较大温度范围内实现高精度的片上温度检测,提出一种基于新型延迟电路的CMOS时域温度传感器。该传感器以新型延迟电路为基础,利用二极管连接的双极结型晶体管（BJT）生成PWM信号,相较于其它时域温度传感器,仅需要单一偏置电流以及比较器就可生成PWM信号;利用简易的数字计数器可确定占空比,且占空比会被转换成数字值;传感器设计采用了0.18 μm CMOS技术。实际测试结果显示,相较于其它类似传感器,提出的传感器在较宽的温度范围内精确度较高;在两个温度点上进行数字校准之后,在0℃~125℃范围内的精确度为±0.1℃;电源为1.5V时,此传感器仅消耗了2.48 μA,功耗为3.8 μW。 关键词：时域温度传感器;延迟电路;低电压低功率;时间数字转换器（TDC）     

一种带有升压电路的0.5 V 3 GHz低功耗LC VCO设计

采用标准的0.13μm CMOS工艺实现了0.5V电源电压,3GHz LC压控振荡器。为了适应低电压工作,并实现低相位噪声,该压控振荡器采用了NMOS差分对的电压偏置振荡器结构,去除尾电流,以尾电感代替,采用感性压控端,增加升压电路结构使变容管的一端升压,这样控制电压变化范围得到扩展。测试结果显示,当电源电压为0.5V,振荡频率为3.126GHz时,在相位噪声为-113.83dBc/Hz@1MHz,调谐范围为12%,核心电路功耗仅1.765mW,该振荡器的归一化品质因数可达-186.2dB,芯片面积为0.96mm×0.9mm。     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².